diff --git a/litex/soc/cores/jtag.py b/litex/soc/cores/jtag.py
index 0441e8c51..2fadcce06 100644
--- a/litex/soc/cores/jtag.py
+++ b/litex/soc/cores/jtag.py
@@ -88,7 +88,7 @@ class USJTAG(XilinxJTAG):
 # JTAG PHY -----------------------------------------------------------------------------------------
 
 class JTAGPHY(Module):
-    def __init__(self, jtag=None, device=None, data_width=8, clock_domain="sys"):
+    def __init__(self, jtag=None, device=None, data_width=8, clock_domain="sys", chain=1):
         """JTAG PHY
 
         Provides a simple JTAG to LiteX stream module to easily stream data to/from the FPGA
@@ -118,11 +118,11 @@ class JTAGPHY(Module):
         # JTAG TAP ---------------------------------------------------------------------------------
         if jtag is None:
             if device[:3] == "xc6":
-                jtag = S6JTAG()
+                jtag = S6JTAG(chain=chain)
             elif device[:3] == "xc7":
-                jtag = S7JTAG()
+                jtag = S7JTAG(chain=chain)
             elif device[:4] in ["xcku", "xcvu"]:
-                jtag = USJTAG()
+                jtag = USJTAG(chain=chain)
             else:
                 raise NotImplementedError
             self.submodules.jtag = jtag
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index d71bbf9c7..f0dba753f 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1203,11 +1203,11 @@ class LiteXSoC(SoC):
         self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
 
     # Add JTAGbone ---------------------------------------------------------------------------------
-    def add_jtagbone(self):
+    def add_jtagbone(self, chain=1):
         from litex.soc.cores import uart
         from litex.soc.cores.jtag import JTAGPHY
         self.check_if_exists("jtabone")
-        self.submodules.jtagbone_phy = JTAGPHY(device=self.platform.device)
+        self.submodules.jtagbone_phy = JTAGPHY(device=self.platform.device, chain=chain)
         self.submodules.jtagbone = uart.UARTBone(phy=self.jtagbone_phy, clk_freq=self.sys_clk_freq)
         self.bus.add_master(name="jtagbone", master=self.jtagbone.wishbone)