diff --git a/README b/README
index 57d0073e6..1bdcefedb 100644
--- a/README
+++ b/README
@@ -7,6 +7,7 @@
florent@enjoy-digital.fr
A small footprint and configurable Ethernet core
+ with UDP/IP hw stack and Etherbone frontend
developed by EnjoyDigital
[> Doc
@@ -41,13 +42,12 @@ by generating the verilog rtl that you will use as a standard core.
- Ethernet MAC with various interfaces and various PHYs (GMII, MII, Loopback)
- Hardware UDP/IP stack with ARP and ICMP
-[> Possibles improvements
+[> Possible improvements
-------------------------
- add standardized interfaces (AXI, Avalon-ST)
- add DMA interface to MAC
-- add hardware Etherbone support
- add RGMII/SGMII PHYs
-- ... See below Support and Consulting :)
+- ... See below Support and consulting :)
If you want to support these features, please contact us at florent [AT]
enjoy-digital.fr. You can also contact our partner on the public mailing list
@@ -56,26 +56,32 @@ devel [AT] lists.m-labs.hk.
[> Getting started
------------------
-1. Install Python3 and Xilinx's Vivado software
+1. Install Python3 and your vendor's software
-2. Obtain Migen and install it:
-(we use EnjoyDigital fork for now until new features are merged
-into upstream Migen)
- git clone https://github.com/enjoy-digital/migen
+2. Obtain Migen and install it:
+ git clone https://github.com/m-labs/migen
cd migen
python3 setup.py install
cd ..
-3. Obtain LiteScope and install it:
+3. Obtain MiSoC and install it:
+ git clone https://github.com/m-labs/misoc --recursive
+ cd misoc
+ python3 setup.py install
+ cd ..
+
+Note: in case you have issues with Migen/MiSoC, please retry
+with our forks at:
+ https://github.com/enjoy-digital/misoc
+ https://github.com/enjoy-digital/migen
+until new features are merged.
+
+4. Obtain LiteScope and install it:
git clone https://github.com/enjoy-digital/litescope
cd litescope
python3 setup.py install
cd ..
-4. Obtain MiSoC:
- git clone https://github.com/m-labs/misoc --recursive
- XXX add setup.py to MiSoC for external use of misoclib?
-
5. Obtain LiteEth
git clone https://github.com/enjoy-digital/liteeth
@@ -83,10 +89,18 @@ into upstream Migen)
python3 make.py all (-s UDPSoCDevel to add LiteScopeLA)
7. Test design (only for KC705 for now):
- go to ./test directory and run:
- change com port in config.py to your com port
try to ping 192.168.1.40
- python3 test_udp.py
+ go to ./test directory:
+ change com port in config.py to your com port
+ run make test_udp
+
+8. Build and load Etherbone design (only for KC705 for now):
+ python3 make.py -t Etherbone
+
+9. Test design (only for KC705 for now):
+ try to ping 192.168.1.40
+ go to ./test directory run:
+ run make test_etherbone
[> Simulations:
Simulations are available in ./liteth/test/:
@@ -101,7 +115,9 @@ into upstream Migen)
make simulation_name
[> Tests :
- An UDP loopback is provided and be controlled with: /test/test_udp.py
+ An UDP loopback example is provided and be controlled with: ./test/test_udp.py
+ An Etherbone example with Wishbone SRAM is provided and can be controlled with:
+ ./test/test_etherbone.py
[> License
-----------
@@ -116,7 +132,7 @@ do them if possible:
- send us bug reports when something goes wrong
- send us the modifications and improvements you have done to LiteEth.
-[> Support and Consulting
+[> Support and consulting
--------------------------
We love open-source hardware and like sharing our designs with others.
diff --git a/doc/source/docs/getting_started/downloads.rst b/doc/source/docs/getting_started/downloads.rst
index aa268e9a6..da9313016 100644
--- a/doc/source/docs/getting_started/downloads.rst
+++ b/doc/source/docs/getting_started/downloads.rst
@@ -3,13 +3,13 @@
====================
Download and install
====================
-1. Install Python3 and Xilinx's Vivado software
+1. Install Python3 and your vendor's software
2. Obtain Migen and install it:
- git clone https://github.com/m-labs/migen
- cd migen
- python3 setup.py install
- -cd ..
+ - cd ..
3. Obtain LiteScope and install it:
- git clone https://github.com/enjoy-digital/litescope
@@ -17,9 +17,17 @@ Download and install
- python3 setup.py install
- cd ..
-4. Obtain MiSoC:
+4. Obtain MiSoC and install it:
- git clone https://github.com/m-labs/misoc --recursive
- XXX add setup.py to MiSoC for external use of misoclib?
+ - cd misoc
+ - python3 setup.py install
+ - cd ..
+
+.. note::
+ In case you have issues with Migen/MiSoC, please retry with our forks at:
+ https://github.com/enjoy-digital/misoc
+ https://github.com/enjoy-digital/migen
+ until new features are merged.
5. Obtain LiteEth
- git clone https://github.com/enjoy-digital/liteeth
@@ -28,7 +36,15 @@ Download and install
- python3 make.py all (-s UDPSoCDevel to add LiteScopeLA)
7. Test design (only for KC705 for now):
- - go to ./test directory and run:
- - change com port in config.py to your com port
- try to ping 192.168.1.40
- - python3 test_udp.py
+ - go to ./test directory:
+ - change com port in config.py to your com port
+ - run make test_udp
+
+8. Build and load Etherbone design (only for KC705 for now):
+ - python3 make.py -t Etherbone
+
+9. Test design (only for KC705 for now):
+ - try to ping 192.168.1.40
+ - go to ./test directory run:
+ - run make test_etherbone
\ No newline at end of file
diff --git a/doc/source/home_page_layout.html b/doc/source/home_page_layout.html
index 4c163f4f2..6c8e98c1b 100644
--- a/doc/source/home_page_layout.html
+++ b/doc/source/home_page_layout.html
@@ -1,6 +1,6 @@
-A small footprint and configurable Ethernet core.
+A small footprint and configurable Ethernet core with UDP/IP hw stack and Etherbone frontend.