diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 5c465d5ad..121d3b691 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1809,15 +1809,16 @@ class LiteXSoC(SoC): def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth", data_width=8, mac_address = 0x10e2d5000000, ip_address = "192.168.1.50", - ethernet_mac_address = 0x10e2d5000001, - ethernet_local_ip = "192.168.1.51", - ethernet_remote_ip = "192.168.1.100", arp_entries = 1, udp_port = 1234, buffer_depth = 16, with_ip_broadcast = True, with_timing_constraints = True, - with_ethmac = False): + with_ethmac = False, + ethmac_address = 0x10e2d5000001, + ethmac_local_ip = "192.168.1.51", + ethmac_remote_ip = "192.168.1.100"): + # Imports from liteeth.core import LiteEthUDPIPCore from liteeth.frontend.etherbone import LiteEthEtherbone @@ -1874,8 +1875,8 @@ class LiteXSoC(SoC): # Ethernet MAC (CPU). if with_ethmac: - assert mac_address != ethernet_mac_address - assert ip_address != ethernet_local_ip + assert mac_address != ethmac_address + assert ip_address != ethmac_local_ip self.check_if_exists("ethmac") ethcore.autocsr_exclude = {"mac"} @@ -1890,9 +1891,9 @@ class LiteXSoC(SoC): self.add_constant("ETH_PHY_NO_RESET") # Disable reset from BIOS to avoid disabling Hardware Interface. - add_ip_address_constants(self, "LOCALIP", ethernet_local_ip) - add_ip_address_constants(self, "REMOTEIP", ethernet_remote_ip) - add_mac_address_constants(self, "MACADDR", ethernet_mac_address) + add_ip_address_constants(self, "LOCALIP", ethmac_local_ip) + add_ip_address_constants(self, "REMOTEIP", ethmac_remote_ip) + add_mac_address_constants(self, "MACADDR", ethmac_address) # Add SPI Flash -------------------------------------------------------------------------------- def add_spi_flash(self, name="spiflash", mode="4x", clk_freq=20e6, module=None, phy=None, rate="1:1", software_debug=False, **kwargs):