diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index c9248057d..e07960be3 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -7,79 +7,114 @@ from litex.gen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import arty -from litex.soc.integration.soc_core import * +from litex.soc.integration.soc_core import mem_decoder +from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * +from litedram.modules import MT41K128M16 +from litedram.phy import a7ddrphy + from liteeth.phy.mii import LiteEthPHYMII from liteeth.core.mac import LiteEthMAC + class _CRG(Module): def __init__(self, platform): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_eth = ClockDomain(reset_less=True) + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) + self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_clk50 = ClockDomain() clk100 = platform.request("clk100") rst = platform.request("cpu_reset") pll_locked = Signal() pll_fb = Signal() - pll_sys = Signal() - pll_eth = Signal() + self.pll_sys = Signal() + pll_sys4x = Signal() + pll_sys4x_dqs = Signal() + pll_clk200 = Signal() + pll_clk50 = Signal() self.specials += [ Instance("PLLE2_BASE", p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, - # VCO @ 800 MHz + # VCO @ 1600 MHz p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0, - p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1, + p_CLKFBOUT_MULT=16, p_DIVCLK_DIVIDE=1, i_CLKIN1=clk100, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, # 100 MHz - p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=pll_sys, + p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0, + o_CLKOUT0=self.pll_sys, - # 25 MHz - p_CLKOUT1_DIVIDE=32, p_CLKOUT1_PHASE=0.0, - o_CLKOUT1=pll_eth, + # 400 MHz + p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0, + o_CLKOUT1=pll_sys4x, + + # 400 MHz dqs + p_CLKOUT2_DIVIDE=4, p_CLKOUT2_PHASE=90.0, + o_CLKOUT2=pll_sys4x_dqs, # 200 MHz - p_CLKOUT2_DIVIDE=4, p_CLKOUT2_PHASE=0.0, - #o_CLKOUT2=, + p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0, + o_CLKOUT3=pll_clk200, - # 200 MHz - p_CLKOUT3_DIVIDE=4, p_CLKOUT3_PHASE=0.0, - #o_CLKOUT3=, - - # 200MHz - p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0, - #o_CLKOUT4= + # 50MHz + p_CLKOUT4_DIVIDE=32, p_CLKOUT4_PHASE=0.0, + o_CLKOUT4=pll_clk50 ), - Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), - Instance("BUFG", i_I=pll_eth, o_O=self.cd_eth.clk), + Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk), + Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), + Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk), + Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk), + Instance("BUFG", i_I=pll_clk50, o_O=self.cd_clk50.clk), AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~rst), + AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst), + AsyncResetSynchronizer(self.cd_clk50, ~pll_locked | ~rst), ] + reset_counter = Signal(4, reset=15) + ic_reset = Signal(reset=1) + self.sync.clk200 += \ + If(reset_counter != 0, + reset_counter.eq(reset_counter - 1) + ).Else( + ic_reset.eq(0) + ) + self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset) + eth_clk = Signal() self.specials += [ - Instance("ODDR2", p_DDR_ALIGNMENT="NONE", - p_INIT=0, p_SRTYPE="SYNC", - i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1, - i_C0=self.cd_eth.clk, i_C1=~self.cd_eth.clk, - o_Q=platform.request("eth_ref_clk")) + Instance("BUFR", p_BUFR_DIVIDE="4", i_CE=1, i_CLR=0, i_I=clk100, o_O=eth_clk), + Instance("BUFG", i_I=eth_clk, o_O=platform.request("eth_ref_clk")), ] -class BaseSoC(SoCCore): +class BaseSoC(SoCSDRAM): + csr_map = { + "ddrphy": 16, + } + csr_map.update(SoCSDRAM.csr_map) def __init__(self, **kwargs): platform = arty.Platform() - SoCCore.__init__(self, platform, clk_freq=100*1000000, + SoCSDRAM.__init__(self, platform, clk_freq=100*1000000, integrated_rom_size=0x8000, integrated_sram_size=0x8000, - integrated_main_ram_size=0x10000, **kwargs) self.submodules.crg = _CRG(platform) + # sdram + self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) + self.add_constant("A7DDRPHY_BITSLIP", 2) + self.add_constant("A7DDRPHY_DELAY", 6) + sdram_module = MT41K128M16(self.clk_freq, "1:4") + self.register_sdram(self.ddrphy, + sdram_module.geom_settings, + sdram_module.timing_settings) + class MiniSoC(BaseSoC): csr_map = { @@ -107,17 +142,27 @@ class MiniSoC(BaseSoC): self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") + self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") + self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 80.0) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 80.0) + self.platform.add_false_path_constraints( + self.crg.cd_sys.clk, + self.ethphy.crg.cd_eth_rx.clk, + self.ethphy.crg.cd_eth_tx.clk) + def main(): parser = argparse.ArgumentParser(description="LiteX SoC port to Arty") builder_args(parser) - soc_core_args(parser) + soc_sdram_args(parser) parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") args = parser.parse_args() cls = MiniSoC if args.with_ethernet else BaseSoC - soc = cls(**soc_core_argdict(args)) + soc = cls(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 16fdf6338..c2900d58f 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -7,9 +7,13 @@ from litex.gen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import nexys_video -from litex.soc.integration.soc_core import * +from litex.soc.integration.soc_core import mem_decoder +from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * +from litedram.modules import MT41K256M16 +from litedram.phy import a7ddrphy + from liteeth.phy.s7rgmii import LiteEthPHYRGMII from liteeth.core.mac import LiteEthMAC @@ -17,36 +21,57 @@ from liteeth.core.mac import LiteEthMAC class _CRG(Module): def __init__(self, platform): self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_clk100 = ClockDomain() clk100 = platform.request("clk100") rst = platform.request("cpu_reset") pll_locked = Signal() pll_fb = Signal() - pll_sys = Signal() + self.pll_sys = Signal() + pll_sys4x = Signal() + pll_sys4x_dqs = Signal() pll_clk200 = Signal() self.specials += [ Instance("PLLE2_BASE", p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, - # VCO @ 800 MHz + # VCO @ 1600 MHz p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0, - p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1, + p_CLKFBOUT_MULT=16, p_DIVCLK_DIVIDE=1, i_CLKIN1=clk100, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, # 100 MHz - p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=pll_sys, + p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0, + o_CLKOUT0=self.pll_sys, + + # 400 MHz + p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0, + o_CLKOUT1=pll_sys4x, + + # 400 MHz dqs + p_CLKOUT2_DIVIDE=4, p_CLKOUT2_PHASE=90.0, + o_CLKOUT2=pll_sys4x_dqs, # 200 MHz - p_CLKOUT3_DIVIDE=4, p_CLKOUT3_PHASE=0.0, - o_CLKOUT3=pll_clk200 + p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0, + o_CLKOUT3=pll_clk200, + + # 400MHz + p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0, + #o_CLKOUT4= ), - Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), + Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk), + Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), + Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk), Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk), + Instance("BUFG", i_I=clk100, o_O=self.cd_clk100.clk), AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~rst), AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst), + AsyncResetSynchronizer(self.cd_clk100, ~pll_locked | rst), ] reset_counter = Signal(4, reset=15) @@ -60,17 +85,29 @@ class _CRG(Module): self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset) -class BaseSoC(SoCCore): +class BaseSoC(SoCSDRAM): + csr_map = { + "ddrphy": 16, + } + csr_map.update(SoCSDRAM.csr_map) def __init__(self, **kwargs): platform = nexys_video.Platform() - SoCCore.__init__(self, platform, clk_freq=100*1000000, + SoCSDRAM.__init__(self, platform, clk_freq=100*1000000, integrated_rom_size=0x8000, integrated_sram_size=0x8000, - integrated_main_ram_size=0x10000, **kwargs) self.submodules.crg = _CRG(platform) + # sdram + self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) + self.add_constant("A7DDRPHY_BITSLIP", 2) + self.add_constant("A7DDRPHY_DELAY", 8) + sdram_module = MT41K256M16(self.clk_freq, "1:4") + self.register_sdram(self.ddrphy, + sdram_module.geom_settings, + sdram_module.timing_settings) + class MiniSoC(BaseSoC): csr_map = { @@ -98,16 +135,27 @@ class MiniSoC(BaseSoC): self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") + self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") + self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) + self.platform.add_false_path_constraints( + self.crg.cd_sys.clk, + self.ethphy.crg.cd_eth_rx.clk, + self.ethphy.crg.cd_eth_tx.clk) + + def main(): parser = argparse.ArgumentParser(description="LiteX SoC port to Nexys Video") builder_args(parser) - soc_core_args(parser) + soc_sdram_args(parser) parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") args = parser.parse_args() cls = MiniSoC if args.with_ethernet else BaseSoC - soc = cls(**soc_core_argdict(args)) + soc = cls(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build()