From b0192e5f8bb6f1d97a2d023bbf9f947b77c19c8c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 10 Jul 2019 10:37:32 +0200 Subject: [PATCH] soc_core: use fixed 16MB CSR address space Using too small CSR address space cause a regression on PCIe SoC, this would need to be understood if we want to reduce CSR address space under 16MB. --- litex/soc/integration/soc_core.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 0e0a30174..5de233c78 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -298,7 +298,8 @@ class SoCCore(Module): self.add_csr_master(self.wishbone2csr.csr) self.config["CSR_DATA_WIDTH"] = csr_data_width self.config["CSR_ALIGNMENT"] = csr_alignment - self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 2**(csr_address_width + 2)) + assert 2**(csr_address_width + 2) <= 0x1000000 + self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 0x1000000) # Add UART if with_uart: