From b031c5edae11636fea84de7f0d4198c733f2c131 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 27 Feb 2015 17:12:37 +0100 Subject: [PATCH] targets: fix MiniSoC --- targets/kc705.py | 2 +- targets/mlabs_video.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/kc705.py b/targets/kc705.py index 6f278399a..ddbe406f7 100644 --- a/targets/kc705.py +++ b/targets/kc705.py @@ -131,6 +131,6 @@ class MiniSoC(BaseSoC): self.submodules.ethphy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) - self.add_cpu_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000) + self.add_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000) default_subtarget = BaseSoC diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index dc4d58cb2..a6dab0a6f 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -101,7 +101,7 @@ class MiniSoC(BaseSoC): self.submodules.ethphy = LiteEthPHYMII(platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) - self.add_cpu_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000) + self.add_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000) def get_vga_dvi(platform): try: