From b0578580714ad7d298e244fc3835c06ba082f2c1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 5 May 2020 16:58:33 +0200 Subject: [PATCH] gen/fhdl/verilog: explicitly define input/output/inout wires. When integrating designs which set `default_nettype none, the top also needs to explicitly define the type of the signals. --- litex/gen/fhdl/verilog.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index f515dbfb2..98a732707 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -236,17 +236,17 @@ def _printheader(f, ios, name, ns, attr_translate, sig.type = "wire" if sig in inouts: sig.direction = "inout" - r += "\tinout " + _printsig(ns, sig) + r += "\tinout wire " + _printsig(ns, sig) elif sig in targets: sig.direction = "output" if sig in wires: - r += "\toutput " + _printsig(ns, sig) + r += "\toutput wire " + _printsig(ns, sig) else: sig.type = "reg" r += "\toutput reg " + _printsig(ns, sig) else: sig.direction = "input" - r += "\tinput " + _printsig(ns, sig) + r += "\tinput wire " + _printsig(ns, sig) r += "\n);\n\n" for sig in sorted(sigs - ios, key=lambda x: x.duid): attr = _printattr(sig.attr, attr_translate)