From b092d2a1806af494c6199f06aefee9424778342e Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 3 Mar 2022 16:45:20 +0100
Subject: [PATCH] cores/jtag: Fix chain parameter on XilinxJTAG.

---
 litex/soc/cores/jtag.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/cores/jtag.py b/litex/soc/cores/jtag.py
index b7ce1f990..d3c3c553f 100644
--- a/litex/soc/cores/jtag.py
+++ b/litex/soc/cores/jtag.py
@@ -401,7 +401,7 @@ class JTAGPHY(Module):
         if jtag is None:
             # Xilinx.
             if XilinxJTAG.get_primitive(device) is not None:
-                jtag = XilinxJTAG(primitive=XilinxJTAG.get_primitive(device))
+                jtag = XilinxJTAG(primitive=XilinxJTAG.get_primitive(device), chain=chain)
             # Lattice.
             elif device[:5] == "LFE5U":
                 jtag = ECP5JTAG()