From b0b57491bb2819047886ad211335b793d9297b93 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Fri, 28 Oct 2022 11:26:06 +1030 Subject: [PATCH] test_cpu: Add Microwatt to tested CPUs Now that LiteX can convert from VHDL to Verilog using GHDL, and the required dependencies are installed in the CI environment, start testing Microwatt. Signed-off-by: Joel Stanley --- test/test_cpu.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/test_cpu.py b/test/test_cpu.py index 43a8a56e7..41382b5d0 100644 --- a/test/test_cpu.py +++ b/test/test_cpu.py @@ -45,6 +45,7 @@ class TestCPU(unittest.TestCase): "serv", # (riscv / softcore) "vexriscv", # (riscv / softcore) "vexriscv_smp", # (riscv / softcore) + "microwatt", # (ppc64 / softcore) ] untested_cpus = [ "blackparrot", # (riscv / softcore) -> Broken install? @@ -57,7 +58,6 @@ class TestCPU(unittest.TestCase): "gowin_emcu", # (arm / hardcore) -> Hardcore. "ibex", # (riscv / softcore) -> Broken since 2022.11.12. "lm32", # (lm32 / softcore) -> Requires LM32 toolchain. - "microwatt", # (ppc64 / softcore) -> Requires PPC toolchain + VHDL->Verilog (GHDL + Yosys). "minerva", # (riscv / softcore) -> Broken install? (Amaranth?) "mor1kx", # (or1k / softcore) -> Verilator compilation issue. "neorv32", # (riscv / softcore) -> Requires VHDL->Verilog (GHDL + Yosys).