From b145f9e5e2b0e1936fb19d3b483c718b64594696 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 8 Jun 2012 17:52:32 +0200 Subject: [PATCH] sim: multiread/multiwrite --- migen/sim/generic.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/migen/sim/generic.py b/migen/sim/generic.py index 323f62ff2..d503289a8 100644 --- a/migen/sim/generic.py +++ b/migen/sim/generic.py @@ -139,7 +139,28 @@ class Simulator: value += 2**nbits assert(value >= 0 and value < 2**nbits) self.ipc.send(MessageWrite(name, Int32(index), value)) + + def multiread(self, obj): + if isinstance(obj, Signal): + return self.rd(obj) + elif isinstance(obj, list): + return [self.multiread(item) for item in obj] + elif hasattr(obj, "__dict__"): + return dict([(k, self.multiread(v)) for k, v in obj.__dict__.items()]) + + def multiwrite(self, obj, value): + if isinstance(obj, Signal): + self.wr(obj, value) + elif isinstance(obj, list): + for target, source in zip(obj, value): + self.multiwrite(target, source) + else: + for k, v in value.items(): + self.multiwrite(getattr(obj, k), v) + +# Contrary to multiread/multiwrite, Proxy fetches the necessary signals only and +# immediately forwards writes into the simulation. class Proxy: def __init__(self, sim, obj): self.__dict__["_sim"] = sim