From b1ea3340f31860ad81fc20165af5895a3cdefd32 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 22 Jul 2015 22:55:11 +0200 Subject: [PATCH] litepcie/frontend/dma: add loop counter (useful to detect missed interrupts) --- misoclib/com/litepcie/frontend/dma/common.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/misoclib/com/litepcie/frontend/dma/common.py b/misoclib/com/litepcie/frontend/dma/common.py index 8db28463a..e54846cd5 100644 --- a/misoclib/com/litepcie/frontend/dma/common.py +++ b/misoclib/com/litepcie/frontend/dma/common.py @@ -30,6 +30,7 @@ class DMARequestTable(Module, AutoCSR): self._loop_prog_n = CSRStorage() self._index = CSRStatus(log2_int(depth)) self._level = CSRStatus(log2_int(depth)) + self._loop = CSRStatus(16) self._flush = CSR() self.irq = Signal() @@ -41,6 +42,7 @@ class DMARequestTable(Module, AutoCSR): we = self._we.r & self._we.re loop_prog_n = self._loop_prog_n.storage index = self._index.status + loop = self._loop.status level = self._level.status flush = self._flush.r & self._flush.re @@ -86,10 +88,12 @@ class DMARequestTable(Module, AutoCSR): # "loop" mode self.sync += \ If(flush, - index.eq(0) + index.eq(0), + loop.eq(0), ).Elif(source.stb & source.ack, If(fifo.dout.start, - index.eq(0) + index.eq(0), + loop.eq(loop+1) ).Else( index.eq(index+1) )