From b2053b7c52c31d0e99c485493d2f11f0f16b4c68 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 10 Feb 2023 11:35:13 +0100 Subject: [PATCH] cores/dna: Reduce default clk_divider to 2. To fix https://github.com/enjoy-digital/litex/issues/1516. --- litex/soc/cores/dna.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/litex/soc/cores/dna.py b/litex/soc/cores/dna.py index d606fbc68..21ef5f861 100644 --- a/litex/soc/cores/dna.py +++ b/litex/soc/cores/dna.py @@ -13,11 +13,10 @@ from litex.gen import * from litex.soc.interconnect.csr import * - # Xilinx DNA (Device Identifier) ------------------------------------------------------------------- class XilinxDNA(Module, AutoCSR): - def __init__(self, nbits=57, primitive="DNA_PORT", clk_divider=16): + def __init__(self, nbits=57, primitive="DNA_PORT", clk_divider=2): self.nbits = nbits self.clk_divider = clk_divider self._id = CSRStatus(nbits)