From b2e4b221456a4b66b2bc17c4e4354581f5f0a1b5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 30 Jul 2023 15:12:01 +0200 Subject: [PATCH] soc/add_pcie: Add with_ptm parameter and update CHANGES. --- CHANGES.md | 1 + litex/soc/integration/soc.py | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/CHANGES.md b/CHANGES.md index 13913636d..dfa194fde 100644 --- a/CHANGES.md +++ b/CHANGES.md @@ -51,6 +51,7 @@ - liteeth_gen : Added raw UDP port support. - build/vivado : Added .dcp generation also after synthesis and placement. - gen: : Added initial LiteXContext to easily get build properties (platform, device, toolchain, etc...) + - litepcie/endpoint/tlp : Added optional Configuration/PTM TLP support to Packetizer/Depacketizer. [> Changed ---------- diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index fc749cb8e..b13066daf 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -2001,6 +2001,7 @@ class LiteXSoC(SoC): with_dma_monitor = False, with_dma_status = False, with_msi = True, msi_type="msi", msi_width=32, + with_ptm = False, ): # Imports from litepcie.phy.uspciephy import USPCIEPHY @@ -2017,7 +2018,8 @@ class LiteXSoC(SoC): endpoint = LitePCIeEndpoint(phy, max_pending_requests = max_pending_requests, endianness = phy.endianness, - address_width = address_width + address_width = address_width, + with_ptm = with_ptm, ) self.add_module(name=f"{name}_endpoint", module=endpoint)