From b2f32ad124ffd333074f86bc705562910c824630 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 17 Mar 2015 01:07:44 +0100 Subject: [PATCH] targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains) --- targets/simple.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/simple.py b/targets/simple.py index eb8e183f1..7d1617118 100644 --- a/targets/simple.py +++ b/targets/simple.py @@ -1,5 +1,6 @@ from migen.fhdl.std import * from migen.bus import wishbone +from migen.genlib.io import CRG from misoclib.soc import SoC, mem_decoder from misoclib.com.liteeth.phy import LiteEthPHY @@ -12,6 +13,7 @@ class BaseSoC(SoC): with_rom=True, with_main_ram=True, main_ram_size=16*1024, **kwargs) + self.submodules.crg = CRG(platform.request(platform.default_clk_name)) class MiniSoC(BaseSoC): csr_map = {