From b2f8fa5464840f51ba7d8fc783ef0fffb1463b50 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 15 Jul 2021 16:48:24 +0200 Subject: [PATCH] gen/fhdl/verilog: Make DummyAttrTranslate a dict. --- litex/gen/fhdl/verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index 4c581d86f..b7258b1a4 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -369,7 +369,7 @@ def _printspecials(overrides, specials, ns, add_data_file, attr_translate): return r -class DummyAttrTranslate: +class DummyAttrTranslate(dict): def __getitem__(self, k): return (k, "true")