From b30dd0b5c66cd01f58d353703c85977278ac40bb Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 21 Nov 2022 14:32:51 +1030 Subject: [PATCH] test_cpu: Add NeoRV32 to tested CPUs With CI supporting GHDL to convert VHDL to Verilog the neorv32 simulation can be tested. Fixes https://github.com/enjoy-digital/litex/issues/1320 Signed-off-by: Joel Stanley --- test/test_cpu.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/test_cpu.py b/test/test_cpu.py index 41382b5d0..37f5760a9 100644 --- a/test/test_cpu.py +++ b/test/test_cpu.py @@ -42,6 +42,7 @@ class TestCPU(unittest.TestCase): "firev", # (riscv / softcore) "marocchino", # (or1k / softcore) "naxriscv", # (riscv / softcore) + "neorv32", # (riscv / softcore) "serv", # (riscv / softcore) "vexriscv", # (riscv / softcore) "vexriscv_smp", # (riscv / softcore) @@ -60,7 +61,6 @@ class TestCPU(unittest.TestCase): "lm32", # (lm32 / softcore) -> Requires LM32 toolchain. "minerva", # (riscv / softcore) -> Broken install? (Amaranth?) "mor1kx", # (or1k / softcore) -> Verilator compilation issue. - "neorv32", # (riscv / softcore) -> Requires VHDL->Verilog (GHDL + Yosys). "picorv32", # (riscv / softcore) -> Verilator compilation issue. "rocket", # (riscv / softcore) -> Not enough RAM in CI. "zynq7000", # (arm / hardcore) -> Hardcore.