From b31d0f37db5923fe2d516062c7e8cf9576c6680d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 10 Dec 2017 03:01:53 +0100 Subject: [PATCH] cpu/picorv32: adapt to current version, some cleanup --- litex/soc/cores/cpu/picorv32/core.py | 35 +++++++++++++++++++--------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index 12534cee4..3e9464366 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -22,7 +22,9 @@ class PicoRV32(Module): mem_rdata = Signal(32) self.specials += Instance("picorv32", + # parameters p_ENABLE_COUNTERS=1, + p_ENABLE_COUNTERS64=1, p_ENABLE_REGS_16_31=1, p_ENABLE_REGS_DUALPORT=1, p_LATCHED_MEM_RDATA=0, @@ -33,17 +35,25 @@ class PicoRV32(Module): p_CATCH_ILLINSN=1, p_ENABLE_PCPI=0, p_ENABLE_MUL=0, + p_ENABLE_FAST_MUL=0, p_ENABLE_IRQ=0, p_ENABLE_IRQ_QREGS=1, p_ENABLE_IRQ_TIMER=1, + p_ENABLE_TRACE=0, p_MASKED_IRQ=0x00000000, p_LATCHED_IRQ=0xffffffff, p_PROGADDR_RESET=progaddr_reset, p_PROGADDR_IRQ=0x00000010, + p_STACKADDR=0xffffffff, + # clock / reset i_clk=ClockSignal(), i_resetn=~ResetSignal(), + # trap + o_trap=Signal(), # not used + + # memory interface o_mem_valid=mem_valid, o_mem_instr=mem_instr, i_mem_ready=mem_ready, @@ -53,25 +63,28 @@ class PicoRV32(Module): o_mem_wstrb=mem_wstrb, i_mem_rdata=mem_rdata, - o_mem_la_read=Signal(), # Not used - o_mem_la_write=Signal(), # Not used - o_mem_la_addr=Signal(32), # Not used - o_mem_la_wdata=Signal(32), # Not used - o_mem_la_wstrb=Signal(4), # Not used + # look ahead interface (not used) + o_mem_la_read=Signal(), + o_mem_la_write=Signal(), + o_mem_la_addr=Signal(32), + o_mem_la_wdata=Signal(32), + o_mem_la_wstrb=Signal(4), - o_pcpi_valid=Signal(), # Not used - o_pcpi_insn=Signal(32), # Not used - o_pcpi_rs1=Signal(32), # Not used - o_pcpi_rs2=Signal(32), # Not used + # co-processor interface (not used) + o_pcpi_valid=Signal(), + o_pcpi_insn=Signal(32), + o_pcpi_rs1=Signal(32), + o_pcpi_rs2=Signal(32), i_pcpi_wr=0, i_pcpi_rd=0, i_pcpi_wait=0, i_pcpi_ready=0, + # irq interface i_irq=self.interrupt, - o_eoi=Signal(32)) # Not used + o_eoi=Signal(32)) # not used - # adapt mem interface to wishbone + # adapt memory interface to wishbone self.comb += [ # instruction i.adr.eq(mem_addr[2:]),