diff --git a/litex/soc/interconnect/axi/axi_common.py b/litex/soc/interconnect/axi/axi_common.py
index 64e269b3f..a0744e905 100644
--- a/litex/soc/interconnect/axi/axi_common.py
+++ b/litex/soc/interconnect/axi/axi_common.py
@@ -72,6 +72,8 @@ def connect_to_pads(bus, pads, mode="master", axi_full=False):
         if channel in ["w", "r"] and axi_full:
             sig_list += [("last",  1)]
         for name, width in sig_list:
+            if (name == "dest"):
+                continue # No DEST.
             if (channel == "w") and (name == "id") and (bus.version == "axi4"):
                 continue # No WID on AXI4.
             sig  = getattr(ch, name)
diff --git a/litex/soc/interconnect/axi/axi_full.py b/litex/soc/interconnect/axi/axi_full.py
index 3595e93a0..6f607c244 100644
--- a/litex/soc/interconnect/axi/axi_full.py
+++ b/litex/soc/interconnect/axi/axi_full.py
@@ -120,6 +120,8 @@ class AXIInterface:
             channel_layout = (getattr(self, channel).description.payload_layout +
                               getattr(self, channel).description.param_layout)
             for name, width in channel_layout:
+                if (name == "dest"):
+                    continue # No DEST.
                 if (channel == "w") and (name == "id") and (self.version == "axi4"):
                     continue # No WID on AXI4.
                 subsignals.append(Subsignal(channel + name, Pins(width)))