From b356204f952f2184d168d35f026db5200d18c4a7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 6 Sep 2019 11:56:42 +0200 Subject: [PATCH] soc_core: add JTAG UART support (uart_name="jtag_uart) --- litex/soc/integration/soc_core.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index e46e7c615..a8832da0c 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -318,6 +318,9 @@ class SoCCore(Module): if uart_name == "jtag_atlantic": from litex.soc.cores.jtag import JTAGAtlantic self.submodules.uart_phy = JTAGAtlantic() + elif uart_name == "jtag_uart": + from litex.soc.cores.jtag import JTAGPHY + self.submodules.uart_phy = JTAGPHY(device=platform.device) else: self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate) self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))