From b367c27191511f36b10ec4103198978f86f9502c Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 12 Apr 2023 19:54:01 +0200
Subject: [PATCH] integration/soc/zynq: Revert previous commit (incorrect),
 re-enable CSR decode on Zynq7000/MP and add check/error when SoCBusHandler
 has more than one Region and one of them has its decoder disabled.

This will prevent silent errors and means offset needs to be added in Software.
---
 litex/soc/cores/cpu/zynq7000/core.py |  2 +-
 litex/soc/cores/cpu/zynqmp/core.py   |  2 +-
 litex/soc/integration/soc.py         | 22 ++++++++++------------
 3 files changed, 12 insertions(+), 14 deletions(-)

diff --git a/litex/soc/cores/cpu/zynq7000/core.py b/litex/soc/cores/cpu/zynq7000/core.py
index 12426a8f7..cd5de084a 100644
--- a/litex/soc/cores/cpu/zynq7000/core.py
+++ b/litex/soc/cores/cpu/zynq7000/core.py
@@ -31,7 +31,7 @@ class Zynq7000(CPU):
     linker_output_format = "elf32-littlearm"
     nop                  = "nop"
     io_regions           = {0x4000_0000: 0xbc00_0000} # Origin, Length.
-    csr_decode           = False # AXI address is decoded in AXI2Wishbone (target level).
+    csr_decode           = True # AXI address is decoded in AXI2Wishbone, offset needs to be added in Software.
 
     # Memory Mapping.
     @property
diff --git a/litex/soc/cores/cpu/zynqmp/core.py b/litex/soc/cores/cpu/zynqmp/core.py
index efc5d9e2d..3be75ff76 100644
--- a/litex/soc/cores/cpu/zynqmp/core.py
+++ b/litex/soc/cores/cpu/zynqmp/core.py
@@ -27,7 +27,7 @@ class ZynqMP(CPU):
         0x8000_0000: 0x00_4000_0000,
         0xe000_0000: 0xff_2000_0000  # TODO: there are more details here
     }
-    csr_decode           = False # AXI address is decoded in AXI2Wishbone (target level).
+    csr_decode           = True # AXI address is decoded in AXI2Wishbone, offset needs to be added in Software.
 
     @property
     def mem_map(self):
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index b2f9c172c..698fab697 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -490,18 +490,16 @@ class SoCBusHandler(LiteXModule):
                     slave  = next(iter(self.slaves.values())))
             # Otherwise, use InterconnectShared/Crossbar.
             else:
-                # If one region has the decoder disabled, force interconnect to crossbar since shared
-                # interconnect relies on the fact that all regions have decoder to optimize logic.
-                force_crossbar = False
-                for region in self.regions.values():
-                    if region.decode == False:
-                        force_crossbar = True
-                if force_crossbar:
-                    self.logger.info("{} interconnect to {}.".format(
-                        colorer("Forcing"),
-                        colorer("Crossbar"),
-                    ))
-                    self.interconnect = "crossbar"
+                # Check Region decoder use.
+                if len(self.regions) > 1:
+                    for region in self.regions.values():
+                        if region.decode == False:
+                            self.logger.error("Only {} Region can be used when {} Decoder.".format(
+                                colorer("one",       color="red"),
+                                colorer("disabling", color="red"),
+                            ))
+                            self.logger.error(self)
+                            raise SoCError()
                 # Interconnect Logic.
                 interconnect_cls = {
                     "shared"  : interconnect_shared_cls,