From b4ba2a47ef86dcf723e200e4842ba1912430b371 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 17 Jan 2020 06:32:00 +0100 Subject: [PATCH] soc/cores/uart: set rx_fifo_rx_we to True on UARTCrossover --- litex/soc/cores/uart.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index 99261f835..fc4ec27f2 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -272,7 +272,7 @@ class UARTCrossover(UART): def __init__(self, **kwargs): assert kwargs.get("phy", None) == None UART.__init__(self, **kwargs) - self.submodules.xover = UART(tx_fifo_depth=2, rx_fifo_depth=2, rx_fifo_rx_we=False) + self.submodules.xover = UART(tx_fifo_depth=2, rx_fifo_depth=2, rx_fifo_rx_we=True) self.comb += [ self.source.connect(self.xover.sink), self.xover.source.connect(self.sink)