diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index db6204cac..f32f9a871 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -188,7 +188,6 @@ class SimSoC(SoCCore):
                 phy                     = self.sdrphy,
                 module                  = sdram_module,
                 origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
                 l2_cache_size           = kwargs.get("l2_size", 8192),
                 l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
                 l2_cache_reverse        = False