From b52dcde9ba0d5f3b0789229e0091bcec4051f07f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 7 Nov 2019 09:00:54 +0100 Subject: [PATCH] soc_sdram/kcu105: add optional main_ram_size_limit and use it on KCU105 to limit to 1GB instead of 2GB. CSR map will need to be updated to support the 2GB. --- litex/boards/targets/kcu105.py | 4 ++-- litex/soc/integration/soc_sdram.py | 4 +++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index a48c86c15..de12b48f4 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -96,8 +96,8 @@ class BaseSoC(SoCSDRAM): sdram_module = EDY4016A(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, - sdram_module.timing_settings) - + sdram_module.timing_settings, + main_ram_size_limit=0x40000000) # EthernetSoC ------------------------------------------------------------------------------------------ diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index a8ac01edb..c5db62b5b 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -42,7 +42,7 @@ class SoCSDRAM(SoCCore): raise FinalizeError self._wb_sdram_ifs.append(interface) - def register_sdram(self, phy, geom_settings, timing_settings, **kwargs): + def register_sdram(self, phy, geom_settings, timing_settings, main_ram_size_limit=None, **kwargs): assert not self._sdram_phy self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning @@ -62,6 +62,8 @@ class SoCSDRAM(SoCCore): main_ram_size = 2**(geom_settings.bankbits + geom_settings.rowbits + geom_settings.colbits)*phy.settings.databits//8 + if main_ram_size_limit is not None: + main_ram_size = min(main_ram_size, main_ram_size_limit) # SoC [<--> L2 Cache] <--> LiteDRAM ---------------------------------------------------- if self.cpu.name == "rocket":