From b5a9106f56ab56053558b9b6f59c7b60ee4a7d39 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 27 Oct 2023 18:07:22 +0200 Subject: [PATCH] cores/video: Simplify VTG/DMA synchronization and re-synchronize on each end of frame. --- litex/soc/cores/video.py | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/litex/soc/cores/video.py b/litex/soc/cores/video.py index 30096931b..942ecba4a 100644 --- a/litex/soc/cores/video.py +++ b/litex/soc/cores/video.py @@ -693,20 +693,14 @@ class VideoFrameBuffer(LiteXModule): video_pipe_source = self.cdc.source # Video Synchronization/Generation. - fsm = FSM(reset_state="VTG-SYNC") + fsm = FSM(reset_state="SYNC") fsm = ClockDomainsRenamer(clock_domain)(fsm) fsm = ResetInserter()(fsm) self.submodules += fsm self.specials += MultiReg(self.dma.fsm.reset, fsm.reset, clock_domain) - fsm.act("VTG-SYNC", - vtg_sink.ready.eq(1), + fsm.act("SYNC", + vtg_sink.ready.eq(~fsm.reset), If(vtg_sink.valid & vtg_sink.last, - NextState("DMA-SYNC") - ) - ) - fsm.act("DMA-SYNC", - video_pipe_source.ready.eq(1), - If(video_pipe_source.valid & video_pipe_source.last, NextState("RUN") ) ) @@ -715,10 +709,13 @@ class VideoFrameBuffer(LiteXModule): If(vtg_sink.valid & vtg_sink.de, video_pipe_source.connect(source, keep={"valid", "ready"}), vtg_sink.ready.eq(source.valid & source.ready), - + If(video_pipe_source.valid & video_pipe_source.last, + NextState("SYNC") + ) ), vtg_sink.connect(source, keep={"de", "hsync", "vsync"}), ) + if (depth == 32): self.comb += [ source.r.eq(video_pipe_source.data[ 0: 8]),