From b603eaf7d4e924d15dcad8a9693cf4df2e88a8df Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Thu, 28 Mar 2013 20:45:42 +0100
Subject: [PATCH] m1crg: allow up to 150MHz pixel clock

---
 verilog/m1crg/m1crg.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/verilog/m1crg/m1crg.v b/verilog/m1crg/m1crg.v
index bf91d2be9..8d9bf31ed 100644
--- a/verilog/m1crg/m1crg.v
+++ b/verilog/m1crg/m1crg.v
@@ -267,7 +267,7 @@ assign eth_tx_clk = eth_tx_clk_pad;
 DCM_CLKGEN #(
 	.CLKFXDV_DIVIDE(2),
 	.CLKFX_DIVIDE(4),
-	.CLKFX_MD_MAX(2.0),
+	.CLKFX_MD_MAX(3.0),
 	.CLKFX_MULTIPLY(2),
 	.CLKIN_PERIOD(20.0),
 	.SPREAD_SPECTRUM("NONE"),