diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
index 236dba4b4..6aeb6ba50 100644
--- a/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@ -17,10 +17,12 @@ class CPU(Module):
     linker_output_format = None
     interrupts           = {}
     mem_map              = {}
+    io_regions           = {}
 
 class CPUNone(CPU):
     data_width           = 32
     reset_address        = 0x00000000
+    io_regions           = {0x00000000: 0xf0000000} # origin, length
 
 # CPUS ---------------------------------------------------------------------------------------------
 
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index a340e2db4..55278bbc4 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -198,6 +198,7 @@ class SoCCore(Module):
                 self.comb += self.cpu.reset.eq(self.ctrl.reset)
         else:
             self.add_cpu(cpu.CPUNone())
+            self.soc_io_regions.update(self.cpu.io_regions)
 
         # Add user's interrupts (needs to be done after CPU interrupts are allocated)
         for _name, _id in self.interrupt_map.items():