diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 476eeda14..51d08aa37 100755
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1,5 +1,3 @@
-#!/usr/bin/env python3
-
 # This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
@@ -710,8 +708,8 @@ class SoC(Module):
                 slaves         = bus_slaves,
                 register       = True,
                 timeout_cycles = self.bus.timeout)
-        if hasattr(self, "ctrl") and self.bus.timeout is not None:
-            self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error)
+            if hasattr(self, "ctrl") and self.bus.timeout is not None:
+                self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error)
 
         # SoC CSR Interconnect ---------------------------------------------------------------------
         self.submodules.csr_bankarray = csr_bus.CSRBankArray(self,
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index bf5566b2b..d5feb9990 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -111,6 +111,8 @@ class SoCCore(SoC):
         self.integrated_sram_size       = integrated_sram_size
         self.integrated_main_ram_size   = integrated_main_ram_size
 
+        self.csr_data_width             = csr_data_width
+
         self.with_wishbone              = with_wishbone
         self.wishbone_timeout_cycles    = wishbone_timeout_cycles