diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 33240ff2b..597b2aa2b 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -243,6 +243,9 @@ class SoCCore(Module):
                 self.submodules.uart = uart.UART()
                 if uart_name == "stub":
                     self.comb += self.uart.sink.ready.eq(1)
+            elif uart_name == "bridge":
+                self.submodules.uart = uart.UARTWishboneBridge(platform.request("serial"), clk_freq, uart_baudrate)
+                self.add_wb_master(self.uart.wishbone)
             elif uart_name == "crossover":
                 self.submodules.uart = uart.UARTCrossover()
             else: