From b69f2993e41d3fa881398a28c420a8018d38bf46 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 31 Jan 2020 15:12:18 +0100 Subject: [PATCH] soc_core: add UART bridge support (simplify having to do it externally) --- litex/soc/integration/soc_core.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 33240ff2b..597b2aa2b 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -243,6 +243,9 @@ class SoCCore(Module): self.submodules.uart = uart.UART() if uart_name == "stub": self.comb += self.uart.sink.ready.eq(1) + elif uart_name == "bridge": + self.submodules.uart = uart.UARTWishboneBridge(platform.request("serial"), clk_freq, uart_baudrate) + self.add_wb_master(self.uart.wishbone) elif uart_name == "crossover": self.submodules.uart = uart.UARTCrossover() else: