From b6f4302e8e87dae4bdea0c173ab7d2a62833e02e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 15 Jun 2022 19:37:04 +0200 Subject: [PATCH] integration/soc/add_adapter: Add AXI2AXILite and AXI2Wishbone support. --- litex/soc/integration/soc.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 74a0f9673..28cf68554 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -314,8 +314,9 @@ class SoCBusHandler(Module): if interface.data_width != self.data_width: interface_cls = type(interface) converter_cls = { - wishbone.Interface: wishbone.Converter, - axi.AXILiteInterface: axi.AXILiteConverter, + wishbone.Interface : wishbone.Converter, + axi.AXILiteInterface : axi.AXILiteConverter, + axi.AXIInterface : axi.AXIConverter, }[interface_cls] converted_interface = interface_cls(data_width=self.data_width) if direction == "m2s": @@ -346,6 +347,8 @@ class SoCBusHandler(Module): (axi.AXILiteInterface, wishbone.Interface) : axi.AXILite2Wishbone, (wishbone.Interface , axi.AXIInterface) : axi.Wishbone2AXI, (axi.AXILiteInterface, axi.AXIInterface) : axi.AXILite2AXI, + (axi.AXIInterface, axi.AXILiteInterface): axi.AXI2AXILite, + (axi.AXIInterface, wishbone.Interface) : axi.AXI2Wishbone, }[type(master), type(slave)] bridge = bridge_cls(master, slave) self.submodules += bridge