From b7f7c8d159a53be0dbb713b86c658c3b79e023cb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 12 Mar 2018 09:33:05 +0100 Subject: [PATCH] build/xilinx/common/XilinxDDROutputImplS6: DDR_ALIGNMENT="C0" requires SRTYPE to be "ASYNC" --- litex/build/xilinx/common.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py index 8b0986a57..9e90e3426 100644 --- a/litex/build/xilinx/common.py +++ b/litex/build/xilinx/common.py @@ -134,7 +134,7 @@ xilinx_special_overrides = { class XilinxDDROutputImplS6(Module): def __init__(self, i1, i2, o, clk): self.specials += Instance("ODDR2", - p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="SYNC", + p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="ASYNC", i_C0=clk, i_C1=~clk, i_CE=1, i_S=0, i_R=0, i_D0=i1, i_D1=i2, o_Q=o, )