From b8b6ecef7cdfff7a6c5a9344357af6895696be12 Mon Sep 17 00:00:00 2001
From: Richard Tucker <richard.tucker@motec.com.au>
Date: Fri, 10 Feb 2023 12:49:57 +1100
Subject: [PATCH] soc/cores/i2c: fix CSR generation

---
 litex/soc/cores/i2c.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/cores/i2c.py b/litex/soc/cores/i2c.py
index 3c07a4c59..bf1b04bdd 100644
--- a/litex/soc/cores/i2c.py
+++ b/litex/soc/cores/i2c.py
@@ -177,7 +177,7 @@ class I2CMasterMachine(Module):
 #     ("stop",  1),
 #     ("idle",  1),
 # ])
-class I2CMaster(Module):
+class I2CMaster(Module, AutoCSR):
     def __init__(self, pads, bus=None):
         if bus is None:
             bus = wishbone.Interface(data_width=32)