From b8d89535fd72d9c10a15ae7a423a0c63a79bc326 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 29 Mar 2016 14:59:30 +0200 Subject: [PATCH] soc/cores/sdram/phy: fix S6QuarterRateDDRPHY --- litex/soc/cores/sdram/phy/s6ddrphy.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/sdram/phy/s6ddrphy.py b/litex/soc/cores/sdram/phy/s6ddrphy.py index 4678864da..71148bb6a 100644 --- a/litex/soc/cores/sdram/phy/s6ddrphy.py +++ b/litex/soc/cores/sdram/phy/s6ddrphy.py @@ -21,6 +21,7 @@ from operator import or_ from litex.gen import * from litex.gen.genlib.record import * +from litex.gen.fhdl.decorators import ClockDomainsRenamer from litex.soc.interconnect.dfi import * from litex.soc.cores.sdram import settings as sdram_settings @@ -399,7 +400,7 @@ class S6HalfRateDDRPHY(Module): class S6QuarterRateDDRPHY(Module): def __init__(self, pads, rd_bitslip, wr_bitslip, dqs_ddr_alignment): half_rate_phy = S6HalfRateDDRPHY(pads, "DDR3", rd_bitslip, wr_bitslip, dqs_ddr_alignment) - self.submodules += RenameClockDomains(half_rate_phy, {"sys" : "sys2x"}) + self.submodules += ClockDomainsRenamer("sys2x")(half_rate_phy) addressbits = len(pads.a) bankbits = len(pads.ba)