diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index d5017ab29..837252c88 100755
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -408,6 +408,9 @@ class SoCBusHandler(LiteXModule):
             colorer(name,    color="underline"),
             colorer("added", color="green")))
 
+    def add_controller(self, name=None, controller=None):
+        self.add_master(self, name=name, master=controller)
+
     def add_slave(self, name=None, slave=None, region=None):
         no_name   = name is None
         no_region = region is None
@@ -440,6 +443,9 @@ class SoCBusHandler(LiteXModule):
             colorer(name, color="underline"),
             colorer("added", color="green")))
 
+    def add_peripheral(self, name=None, peripheral=None, region=None):
+        self.add_slave(self, name=name, slave=peripheral, region=region)
+
     def get_address_width(self, standard):
         standard_from = self.standard
         standard_to   = standard
diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index 32559d301..00a9f917c 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -149,7 +149,12 @@ class InterconnectPointToPoint(Module):
 
 
 class Arbiter(Module):
-    def __init__(self, masters, target):
+    def __init__(self, masters=None, target=None, controllers=None):
+        assert target is not None
+        assert (masters is not None) or (controllers is not None)
+        if controllers is not None:
+            masters = controllers
+
         self.submodules.rr = roundrobin.RoundRobin(len(masters))
 
         # mux master->slave signals