diff --git a/litex/build/osfpga/__init__.py b/litex/build/osfpga/__init__.py deleted file mode 100644 index 9b874d960..000000000 --- a/litex/build/osfpga/__init__.py +++ /dev/null @@ -1 +0,0 @@ -from litex.build.osfpga.platform import OSFPGAPlatform diff --git a/litex/build/osfpga/common.py b/litex/build/osfpga/common.py deleted file mode 100644 index f5aa89254..000000000 --- a/litex/build/osfpga/common.py +++ /dev/null @@ -1,27 +0,0 @@ -# -# This file is part of LiteX. -# -# Copyright (c) 2022 Florent Kermarrec -# SPDX-License-Identifier: BSD-2-Clause - -from migen.fhdl.module import Module -from migen.genlib.resetsync import AsyncResetSynchronizer - -from litex.build.io import * - -# OS-FPGA AsyncResetSynchronizer ------------------------------------------------------------------- - -class OSFPGAAsyncResetSynchronizerImpl(Module): - def __init__(self, cd, async_reset): - self.comb += cd.rst.eq(async_reset) # FIXME: Implement. - -class OSFPGAAsyncResetSynchronizer: - @staticmethod - def lower(dr): - return OSFPGAAsyncResetSynchronizerImpl(dr.cd, dr.async_reset) - -# OS-FPGA Special Overrides ------------------------------------------------------------------------- - -osfpga_special_overrides = { - AsyncResetSynchronizer: OSFPGAAsyncResetSynchronizer, -} diff --git a/litex/build/osfpga/osfpga.py b/litex/build/osfpga/osfpga.py deleted file mode 100644 index 382e864fc..000000000 --- a/litex/build/osfpga/osfpga.py +++ /dev/null @@ -1,99 +0,0 @@ -# -# This file is part of LiteX. -# -# Copyright (c) 2022 Florent Kermarrec -# SPDX-License-Identifier: BSD-2-Clause - -import os -import sys -import math -import subprocess -from shutil import which, copyfile - -from migen.fhdl.structure import _Fragment - -from litex.build.generic_toolchain import GenericToolchain -from litex.build.generic_platform import * -from litex.build import tools - -# OSFPGAToolchain ---------------------------------------------------------------------------------- - -class OSFPGAToolchain(GenericToolchain): - attr_translate = {} - - def __init__(self, toolchain): - super().__init__() - self.toolchain = toolchain - self.clocks = dict() - - # Constraints ---------------------------------------------------------------------------------- - - def build_io_constraints(self): - return ("", "") # TODO - - # Timing Constraints (.sdc) -------------------------------------------------------------------- - - def build_timing_constraints(self, vns): - sdc = [] - for clk, [period, name] in sorted(self.clocks.items(), key=lambda x: x[0].duid): - clk_sig = self._vns.get_name(clk) - if name is None: - name = clk_sig - sdc.append(f"create_clock -name {name} -period {str(period)} [get_ports {{{clk_sig}}}]") - with open(f"{self._build_name}.sdc", "w") as f: - f.write("\n".join(sdc)) - return (self._build_name + ".sdc", "SDC") - - # Project -------------------------------------------------------------------------------------- - - def build_project(self): - tcl = [] - - # Create Design. - tcl.append(f"create_design {self._build_name}") - - # Set Device. - tcl.append(f"target_device {self.platform.device.upper()}") - - # Add Include Path. - tcl.append("add_include_path ./") - for include_path in self.platform.verilog_include_paths: - tcl.append(f"add_include_path {include_path}") - - # Add Sources. - for f, typ, lib in self.platform.sources: - tcl.append(f"add_design_file {f}") - - # Set Top Module. - tcl.append(f"set_top_module {self._build_name}") - - # Add Timings Constraints. - tcl.append(f"add_constraint_file {self._build_name}.sdc") - - # Run. - tcl.append("synth") - tcl.append("packing") - tcl.append("place") - tcl.append("route") - tcl.append("sta") - tcl.append("power") - tcl.append("bitstream") - - # Generate .tcl. - with open("build.tcl", "w") as f: - f.write("\n".join(tcl)) - - # Script --------------------------------------------------------------------------------------- - - def build_script(self): - return "" # unused - - def run_script(self, script): - toolchain_sh = self.toolchain - if which(toolchain_sh) is None: - msg = f"Unable to find {toolchain_sh.upper()} toolchain, please:\n" - msg += f"- Add {toolchain_sh.upper()} toolchain to your $PATH." - raise OSError(msg) - - if subprocess.call([toolchain_sh, "--batch", "--script", "build.tcl"]) != 0: - raise OSError(f"Error occured during {toolchain_sh.upper()}'s script execution.") diff --git a/litex/build/osfpga/platform.py b/litex/build/osfpga/platform.py deleted file mode 100644 index d3665ae15..000000000 --- a/litex/build/osfpga/platform.py +++ /dev/null @@ -1,39 +0,0 @@ -# -# This file is part of LiteX. -# -# Copyright (c) 2022 Florent Kermarrec -# SPDX-License-Identifier: BSD-2-Clause - -import os - -from litex.build.generic_platform import GenericPlatform -from litex.build.osfpga import common, osfpga - -# OSFPGAPlatform ----------------------------------------------------------------------------------- - -class OSFPGAPlatform(GenericPlatform): - _bitstream_ext = ".bin" - - _supported_toolchains = ["osfpga"] - - def __init__(self, device, *args, toolchain="foedag", devicename=None, **kwargs): - GenericPlatform.__init__(self, device, *args, **kwargs) - self.devicename = devicename - if toolchain in ["foedag", "raptor"]: - self.toolchain = osfpga.OSFPGAToolchain(toolchain=toolchain) - else: - raise ValueError(f"Unknown toolchain {toolchain}") - - def get_verilog(self, *args, special_overrides=dict(), **kwargs): - so = dict(common.osfpga_special_overrides) - so.update(special_overrides) - return GenericPlatform.get_verilog(self, *args, - special_overrides = so, - attr_translate = self.toolchain.attr_translate, - **kwargs) - - def build(self, *args, **kwargs): - return self.toolchain.build(self, *args, **kwargs) - - def add_false_path_constraint(self, from_, to): - pass # FIXME: Implement. diff --git a/litex/build/osfpga/test_blinky.py b/litex/build/osfpga/test_blinky.py deleted file mode 100755 index 7dd79f3ba..000000000 --- a/litex/build/osfpga/test_blinky.py +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/env python3 - -# -# This file is part of LiteX. -# -# Copyright (c) 2022 Florent Kermarrec -# SPDX-License-Identifier: BSD-2-Clause - -import os - -from migen import * - -from litex.build.generic_platform import Pins -from litex.build.osfpga import OSFPGAPlatform - -# Minimal Platform --------------------------------------------------------------------------------- - -_io = [ - ("clk", 0, Pins(1)), - ("led", 0, Pins(1)) -] - -class Platform(OSFPGAPlatform): - def __init__(self): - OSFPGAPlatform.__init__(self, device="gemini", toolchain="raptor", io=_io) - -# Minimal Design ----------------------------------------------------------------------------------- - -platform = Platform() -clk = platform.request("clk") -led = platform.request("led") -module = Module() -module.clock_domains.cd_sys = ClockDomain("sys") -module.comb += module.cd_sys.clk.eq(clk) -counter = Signal(26) -module.comb += led.eq(counter[25]) -module.sync += counter.eq(counter + 1) - -# Build -------------------------------------------------------------------------------------------- - -platform.build(module, build_name="blinky", run=True) diff --git a/litex/build/osfpga/test_soc.py b/litex/build/osfpga/test_soc.py deleted file mode 100755 index 54b0ca8e3..000000000 --- a/litex/build/osfpga/test_soc.py +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/env python3 - -# -# This file is part of LiteX. -# -# Copyright (c) 2022 Florent Kermarrec -# SPDX-License-Identifier: BSD-2-Clause - -from migen import * - -from litex.build.io import CRG -from litex.build.generic_platform import Pins, Subsignal -from litex.build.osfpga import OSFPGAPlatform - -from litex.soc.integration.soc_core import * -from litex.soc.integration.builder import * - -# Platform --------------------------------------------------------------------------------- - -_io = [ - # Clk. - ("clk", 0, Pins(1)), - - # Serial. - ("serial", 0, - Subsignal("tx", Pins(1)), - Subsignal("rx", Pins(1)), - ), -] - -class Platform(OSFPGAPlatform): - def __init__(self, toolchain="raptor", device="gemini"): - OSFPGAPlatform.__init__(self, device=device, toolchain=toolchain, io=_io) - -# BaseSoC ------------------------------------------------------------------------------------------ - -class BaseSoC(SoCCore): - def __init__(self, platform, sys_clk_freq=int(10e6), **kwargs): - # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = CRG(platform.request("clk")) - - # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX Test SoC on OS-FPGA", **kwargs) - -# Build -------------------------------------------------------------------------------------------- - -def main(): - from litex.soc.integration.soc import LiteXSoCArgumentParser - parser = LiteXSoCArgumentParser(description="LiteX Test SoC on OS-FPGA") - target_group = parser.add_argument_group(title="Target options") - target_group.add_argument("--build", action="store_true", help="Build design.") - target_group.add_argument("--toolchain", default="raptor", help="FPGA toolchain.") - target_group.add_argument("--device", default="gemini", help="FPGA device.") - builder_args(parser) - soc_core_args(parser) - args = parser.parse_args() - - platform = Platform(toolchain=args.toolchain, device=args.device) - soc = BaseSoC(platform,**soc_core_argdict(args)) - builder = Builder(soc, **builder_argdict(args)) - if args.build: - builder.build() - -if __name__ == "__main__": - main()