diff --git a/litex/soc/cores/cpu/ibex/core.py b/litex/soc/cores/cpu/ibex/core.py
index f1a08d872..44bda122c 100644
--- a/litex/soc/cores/cpu/ibex/core.py
+++ b/litex/soc/cores/cpu/ibex/core.py
@@ -211,8 +211,16 @@ class Ibex(CPU):
             "ibex_register_file_fpga.sv",
             "ibex_wb_stage.sv",
             "ibex_core.sv",
-            "ibex_top.sv"
+            #"ibex_top.sv" FIXME.
         )
+         # FIXME: Patch ibex_top.sv to fix missing import.
+        if not os.path.exists("ibex_top.sv"):
+            # Get ibex_top source.
+            os.system("cp {src} {dst}".format(src=os.path.join(ibexdir, "rtl", "ibex_top.sv"), dst="ibex_top.sv"))
+            # FIXME: Patch ibex_top
+            os.system(f"patch -p0 < {os.path.dirname(os.path.realpath(__file__))}/ibex_top.patch")
+        platform.add_source("ibex_top.sv")
+
         platform.add_source(os.path.join(ibexdir, "syn", "rtl", "prim_clock_gating.v"))
         platform.add_sources(os.path.join(opentitandir, "hw", "ip", "prim", "rtl"),
             "prim_alert_pkg.sv",
diff --git a/litex/soc/cores/cpu/ibex/ibex_top.patch b/litex/soc/cores/cpu/ibex/ibex_top.patch
new file mode 100644
index 000000000..d83fbccb8
--- /dev/null
+++ b/litex/soc/cores/cpu/ibex/ibex_top.patch
@@ -0,0 +1,12 @@
+diff --git a/ibex_top.sv b/ibex_top.sv
+index c0148ea4e..eaf4d1533 100644
+--- a/ibex_top.sv
++++ b/ibex_top.sv
+@@ -8,6 +8,7 @@
+ `endif
+ 
+ `include "prim_assert.sv"
++`include "prim_ram_1p_pkg.sv"
+ 
+ /**
+  * Top level module of the ibex RISC-V core