From b95e0a19b105751d2868b83e737f767ad90898aa Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 10 Apr 2020 15:50:35 +0200
Subject: [PATCH] altera/common: add DDROutput, DDRInput, SDROutput, SDRInput.

---
 litex/build/altera/common.py | 133 ++++++++++++++++++++++++-----------
 1 file changed, 93 insertions(+), 40 deletions(-)

diff --git a/litex/build/altera/common.py b/litex/build/altera/common.py
index 252f5fbd4..e9adf2a32 100644
--- a/litex/build/altera/common.py
+++ b/litex/build/altera/common.py
@@ -9,45 +9,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex.build.io import *
 
-# DifferentialInput --------------------------------------------------------------------------------
-
-class AlteraDifferentialInputImpl(Module):
-    def __init__(self, i_p, i_n, o):
-        self.specials += [
-            Instance("ALT_INBUF_DIFF",
-                name   = "ibuf_diff",
-                i_i    = i_p,
-                i_ibar = i_n,
-                o_o    = o
-            )
-        ]
-
-
-class AlteraDifferentialInput:
-    @staticmethod
-    def lower(dr):
-        return AlteraDifferentialInputImpl(dr.i_p, dr.i_n, dr.o)
-
-# DifferentialOutput -------------------------------------------------------------------------------
-
-class AlteraDifferentialOutputImpl(Module):
-    def __init__(self, i, o_p, o_n):
-        self.specials += [
-            Instance("ALT_OUTBUF_DIFF",
-                name   = "obuf_diff",
-                i_i    = i,
-                o_o    = o_p,
-                o_obar = o_n
-            )
-        ]
-
-
-class AlteraDifferentialOutput:
-    @staticmethod
-    def lower(dr):
-        return AlteraDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
-
-# AsyncResetSynchronizer ---------------------------------------------------------------------------
+# Common AsyncResetSynchronizer --------------------------------------------------------------------
 
 class AlteraAsyncResetSynchronizerImpl(Module):
     def __init__(self, cd, async_reset):
@@ -75,10 +37,101 @@ class AlteraAsyncResetSynchronizer:
     def lower(dr):
         return AlteraAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
 
+# Common DifferentialInput -------------------------------------------------------------------------
+
+class AlteraDifferentialInputImpl(Module):
+    def __init__(self, i_p, i_n, o):
+        self.specials += [
+            Instance("ALT_INBUF_DIFF",
+                name   = "ibuf_diff",
+                i_i    = i_p,
+                i_ibar = i_n,
+                o_o    = o
+            )
+        ]
+
+
+class AlteraDifferentialInput:
+    @staticmethod
+    def lower(dr):
+        return AlteraDifferentialInputImpl(dr.i_p, dr.i_n, dr.o)
+
+# Common DifferentialOutput ------------------------------------------------------------------------
+
+class AlteraDifferentialOutputImpl(Module):
+    def __init__(self, i, o_p, o_n):
+        self.specials += [
+            Instance("ALT_OUTBUF_DIFF",
+                name   = "obuf_diff",
+                i_i    = i,
+                o_o    = o_p,
+                o_obar = o_n
+            )
+        ]
+
+
+class AlteraDifferentialOutput:
+    @staticmethod
+    def lower(dr):
+        return AlteraDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
+
+# Common DDROutput ---------------------------------------------------------------------------------
+
+class AlteraDDROutputImpl(Module):
+    def __init__(self, i1, i2, o, clk):
+        self.specials += Instance("ALTDDIO_OUT",
+            p_WIDTH    = 1,
+            i_outclock = clk,
+            i_datain_h = i1,
+            i_datain_l = i2,
+            o_dataout  = o,
+        )
+
+
+class AlteraDDROutput:
+    @staticmethod
+    def lower(dr):
+        return AlteraDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
+
+# Common DDRInput ----------------------------------------------------------------------------------
+
+class AlteraDDRInputImpl(Module):
+    def __init__(self, i, o1, o2, clk):
+        self.specials += Instance("ALTDDIO_IN",
+            p_WIDTH     = 1,
+            i_inclock   = clk,
+            i_datain    = i,
+            o_dataout_h = o1,
+            o_dataout_l = o2
+        )
+
+class AlteraDDRInput:
+    @staticmethod
+    def lower(dr):
+        return AlteraDDRInputImpl(dr.i, dr.o1, dr.o2, dr.clk)
+
+# Common SDROutput -------------------------------------------------------------------------------
+
+class AlteraSDROutput:
+    @staticmethod
+    def lower(dr):
+        return AlteraDDROutputImpl(dr.i, dr.i, dr.o, dr.clk)
+
+# Common SDRInput --------------------------------------------------------------------------------
+
+class AlteraSDRInput:
+    @staticmethod
+    def lower(dr):
+        return AlteraDDRInputImpl(dr.i, dr.o, Signal(), dr.clk)
+
 # Special Overrides --------------------------------------------------------------------------------
 
 altera_special_overrides = {
+    AsyncResetSynchronizer: AlteraAsyncResetSynchronizer,
     DifferentialInput:      AlteraDifferentialInput,
     DifferentialOutput:     AlteraDifferentialOutput,
-    AsyncResetSynchronizer: AlteraAsyncResetSynchronizer,
+    DDROutput:              AlteraDDROutput,
+    DDRInput:               AlteraDDRInput,
+    SDROutput:              AlteraSDROutput,
+    SDRInput:               AlteraSDRInput,
 }