diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index 87c9bf8a6..3ace231bc 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -141,7 +141,6 @@ class Microwatt(CPU):
 
             # Fetch
             "fetch1.vhdl",
-            "fetch2.vhdl",
 
             # Instruction/Data Cache
             "cache_ram.vhdl",
diff --git a/litex/soc/cores/cpu/microwatt/xics_wrapper.vhdl b/litex/soc/cores/cpu/microwatt/xics_wrapper.vhdl
index d7d06850e..419950556 100644
--- a/litex/soc/cores/cpu/microwatt/xics_wrapper.vhdl
+++ b/litex/soc/cores/cpu/microwatt/xics_wrapper.vhdl
@@ -166,7 +166,7 @@ begin
 
     xics_ics : entity work.xics_ics
         generic map (
-            SRC_NUM           => 16
+            SRC_NUM           => 256
         )
         port map (
             clk               => clk,
diff --git a/litex_setup.py b/litex_setup.py
index c17957f08..9d0d7de7f 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -52,7 +52,7 @@ repos = [
     ("pythondata-cpu-vexriscv-smp",("https://github.com/litex-hub/", True,  True, None)),
     ("pythondata-cpu-rocket",      ("https://github.com/litex-hub/", False, True, None)),
     ("pythondata-cpu-minerva",     ("https://github.com/litex-hub/", False, True, None)),
-    ("pythondata-cpu-microwatt",   ("https://github.com/litex-hub/", False, True, 0xba76652)),
+    ("pythondata-cpu-microwatt",   ("https://github.com/litex-hub/", False, True, 0xf9807b6)),
     ("pythondata-cpu-blackparrot", ("https://github.com/litex-hub/", False, True, None)),
     ("pythondata-cpu-cv32e40p",    ("https://github.com/litex-hub/", True,  True, None)),
 ]