From b9e0c95c1836f685386a6f24004882a52c98a120 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 30 Dec 2020 16:20:11 +0100 Subject: [PATCH] cpu/microwatt: use 0xf9807b6 and fix compilation, working with IRQs :) Tested with: /arty.py --cpu-type=microwatt --cpu-variant=standard+irq --integrated-rom-size=0x10000 --build --load __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2020 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Dec 30 2020 15:59:16 BIOS CRC passed (fb76e85d) Migen git sha1: d42aa6f LiteX git sha1: 74844db3 --=============== SoC ==================-- CPU: Microwatt @ 100MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 64KiB SRAM: 8KiB L2: 8KiB SDRAM: 262144KiB 16-bit @ 800MT/s (CL-6 CWL-5) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Write latency calibration: m0:0 m1:0 Read leveling: m0, b0: |00000000000000000000000000000000| delays: - m0, b1: |00000000000011111111111111100000| delays: 19+-07 m0, b2: |00000000000000000000000000001111| delays: 30+-02 m0, b3: |00000000000000000000000000000000| delays: - m0, b4: |00000000000000000000000000000000| delays: - m0, b5: |00000000000000000000000000000000| delays: - m0, b6: |00000000000000000000000000000000| delays: - m0, b7: |00000000000000000000000000000000| delays: - best: m0, b01 delays: 19+-07 m1, b0: |00000000000000000000000000000000| delays: - m1, b1: |00000000000011111111111111000000| delays: 19+-07 m1, b2: |00000000000000000000000000001111| delays: 30+-01 m1, b3: |00000000000000000000000000000000| delays: - m1, b4: |00000000000000000000000000000000| delays: - m1, b5: |00000000000000000000000000000000| delays: - m1, b6: |00000000000000000000000000000000| delays: - m1, b7: |00000000000000000000000000000000| delays: - best: m1, b01 delays: 19+-06 Switching SDRAM to hardware control. Memtest at 0x0000000040000000 (2MiB)... Write: 0x40000000-0x40200000 2MiB Read: 0x40000000-0x40200000 2MiB Memtest OK Memspeed at 0x0000000040000000 (2MiB)... Write speed: 32MiB/s Read speed: 54MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex> --- litex/soc/cores/cpu/microwatt/core.py | 1 - litex/soc/cores/cpu/microwatt/xics_wrapper.vhdl | 2 +- litex_setup.py | 2 +- 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index 87c9bf8a6..3ace231bc 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -141,7 +141,6 @@ class Microwatt(CPU): # Fetch "fetch1.vhdl", - "fetch2.vhdl", # Instruction/Data Cache "cache_ram.vhdl", diff --git a/litex/soc/cores/cpu/microwatt/xics_wrapper.vhdl b/litex/soc/cores/cpu/microwatt/xics_wrapper.vhdl index d7d06850e..419950556 100644 --- a/litex/soc/cores/cpu/microwatt/xics_wrapper.vhdl +++ b/litex/soc/cores/cpu/microwatt/xics_wrapper.vhdl @@ -166,7 +166,7 @@ begin xics_ics : entity work.xics_ics generic map ( - SRC_NUM => 16 + SRC_NUM => 256 ) port map ( clk => clk, diff --git a/litex_setup.py b/litex_setup.py index c17957f08..9d0d7de7f 100755 --- a/litex_setup.py +++ b/litex_setup.py @@ -52,7 +52,7 @@ repos = [ ("pythondata-cpu-vexriscv-smp",("https://github.com/litex-hub/", True, True, None)), ("pythondata-cpu-rocket", ("https://github.com/litex-hub/", False, True, None)), ("pythondata-cpu-minerva", ("https://github.com/litex-hub/", False, True, None)), - ("pythondata-cpu-microwatt", ("https://github.com/litex-hub/", False, True, 0xba76652)), + ("pythondata-cpu-microwatt", ("https://github.com/litex-hub/", False, True, 0xf9807b6)), ("pythondata-cpu-blackparrot", ("https://github.com/litex-hub/", False, True, None)), ("pythondata-cpu-cv32e40p", ("https://github.com/litex-hub/", True, True, None)), ]