From ba0dd5728e04d4c24e67354304c70d29f96dfd20 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sat, 27 Oct 2018 16:02:53 -0700 Subject: [PATCH] uart: Enable buffering the FIFO. On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in block RAM rather than consuming a large amount of resources. --- litex/soc/cores/uart.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index 3e88e7ae9..a5305e6a8 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -157,7 +157,7 @@ def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"): fifo = stream.AsyncFIFO([("data", 8)], depth) return ClockDomainsRenamer({"write": sink_cd, "read": source_cd})(fifo) else: - return stream.SyncFIFO([("data", 8)], depth) + return stream.SyncFIFO([("data", 8)], depth, buffered=True) class UART(Module, AutoCSR):