diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py
index 60b0bc991..d47c627b2 100644
--- a/mibuild/platforms/kc705.py
+++ b/mibuild/platforms/kc705.py
@@ -387,6 +387,7 @@ def Platform(*args, toolchain="vivado", **kwargs):
 		raise ValueError
 
 	class RealPlatform(xilinx_platform):
+		identifier = 0x4B37
 		default_clk_name = "clk156"
 		default_clk_period = 6.4
 		bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py
index cc1b619f5..5dfffb1c4 100644
--- a/mibuild/platforms/m1.py
+++ b/mibuild/platforms/m1.py
@@ -119,6 +119,7 @@ _io = [
 ]
 
 class Platform(XilinxISEPlatform):
+	identifier = 0x4D31
 	default_clk_name = "clk50"
 	default_clk_period = 20
 	def __init__(self):
diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py
index df9eac850..4c5f0944c 100644
--- a/mibuild/platforms/mixxeo.py
+++ b/mibuild/platforms/mixxeo.py
@@ -155,6 +155,7 @@ _io = [
 ]
 
 class Platform(XilinxISEPlatform):
+	identifier = 0x4D58
 	default_clk_name = "clk50"
 	default_clk_period = 20
 	def __init__(self):
diff --git a/mibuild/platforms/papilio_pro.py b/mibuild/platforms/papilio_pro.py
index 0ccd8dd11..545b7518b 100644
--- a/mibuild/platforms/papilio_pro.py
+++ b/mibuild/platforms/papilio_pro.py
@@ -50,6 +50,7 @@ _connectors = [
 ]
 
 class Platform(XilinxISEPlatform):
+	identifier = 0x5050
 	default_clk_name = "clk32"
 	default_clk_period = 31.25
 	def __init__(self):