diff --git a/litex/soc/cores/dma.py b/litex/soc/cores/dma.py
index b116c867c..211664df0 100644
--- a/litex/soc/cores/dma.py
+++ b/litex/soc/cores/dma.py
@@ -72,7 +72,7 @@ class WishboneDMAReader(Module, AutoCSR):
             self.add_csr()
 
     def add_csr(self):
-        self._base   = CSRStorage(32)
+        self._base   = CSRStorage(64)
         self._length = CSRStorage(32)
         self._enable = CSRStorage()
         self._done   = CSRStatus()
@@ -158,7 +158,7 @@ class WishboneDMAWriter(Module, AutoCSR):
         self._sink = self.sink
         self.sink  = stream.Endpoint([("data", self.bus.data_width)])
 
-        self._base   = CSRStorage(32)
+        self._base   = CSRStorage(64)
         self._length = CSRStorage(32)
         self._enable = CSRStorage()
         self._done   = CSRStatus()
diff --git a/litex/soc/software/liblitesdcard/sdcard.c b/litex/soc/software/liblitesdcard/sdcard.c
index 9c2a56228..fc9e3ff0a 100644
--- a/litex/soc/software/liblitesdcard/sdcard.c
+++ b/litex/soc/software/liblitesdcard/sdcard.c
@@ -561,7 +561,7 @@ void sdcard_read(uint32_t sector, uint32_t count, uint8_t* buf)
 {
 	/* Initialize DMA Writer */
 	sdblock2mem_dma_enable_write(0);
-	sdblock2mem_dma_base_write((uint32_t) buf);
+	sdblock2mem_dma_base_write((uint64_t) buf);
 	sdblock2mem_dma_length_write(512*count);
 	sdblock2mem_dma_enable_write(1);
 
@@ -594,7 +594,7 @@ void sdcard_write(uint32_t sector, uint32_t count, uint8_t* buf)
 	while (count--) {
 		/* Initialize DMA Reader */
 		sdmem2block_dma_enable_write(0);
-		sdmem2block_dma_base_write((uint32_t) buf);
+		sdmem2block_dma_base_write((uint64_t) buf);
 		sdmem2block_dma_length_write(512);
 		sdmem2block_dma_enable_write(1);