From ba959c832d09a22272c96d68df9078a19258e495 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 14 Nov 2015 00:42:58 +0100 Subject: [PATCH] soc/interconnect: rename packet to stream_packet --- litex/soc/interconnect/{packet.py => stream_packet.py} | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) rename litex/soc/interconnect/{packet.py => stream_packet.py} (98%) diff --git a/litex/soc/interconnect/packet.py b/litex/soc/interconnect/stream_packet.py similarity index 98% rename from litex/soc/interconnect/packet.py rename to litex/soc/interconnect/stream_packet.py index bac7c9150..17c724c44 100644 --- a/litex/soc/interconnect/packet.py +++ b/litex/soc/interconnect/stream_packet.py @@ -8,10 +8,10 @@ from litex.soc.interconnect.stream import * # TODO: move reverse_bytes / Counter def reverse_bytes(signal): - n = (flen(signal)+7)//8 + n = (len(signal)+7)//8 r = [] for i in reversed(range(n)): - r.append(signal[i*8:min((i+1)*8, flen(signal))]) + r.append(signal[i*8:min((i+1)*8, len(signal))]) return Cat(iter(r)) @@ -20,7 +20,7 @@ def reverse_bytes(signal): class Counter(Module): def __init__(self, *args, increment=1, **kwargs): self.value = Signal(*args, **kwargs) - self.width = flen(self.value) + self.width = len(self.value) self.sync += self.value.eq(self.value+increment) class Status(Module): @@ -159,7 +159,7 @@ class Packetizer(Module): # # # - dw = flen(self.sink.data) + dw = len(self.sink.data) header_reg = Signal(header.length*8) header_words = (header.length*8)//dw @@ -244,7 +244,7 @@ class Depacketizer(Module): # # # - dw = flen(sink.data) + dw = len(sink.data) header_words = (header.length*8)//dw