From bb355a773a92a0204de7cf85eb954bcd6c850ca9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 28 Apr 2021 16:58:11 +0200 Subject: [PATCH] integration/soc/video: Allow passing timings as str or tuple (name, dict). When passed as str, the timing dict will be extracted from litex.soc.cores.video.video_timings. When passed as tuple, custom dict will be directly passed to VTG. --- litex/soc/integration/soc.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 276bb91d8..8f5faec12 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1673,7 +1673,7 @@ class LiteXSoC(SoC): # Video Timing Generator. self.check_if_exists(f"{name}_vtg") - vtg = VideoTimingGenerator(default_video_timings=timings) + vtg = VideoTimingGenerator(default_video_timings=timings if isinstance(timings, str) else timings[1]) vtg = ClockDomainsRenamer(clock_domain)(vtg) setattr(self.submodules, f"{name}_vtg", vtg) @@ -1695,11 +1695,12 @@ class LiteXSoC(SoC): # Video Timing Generator. self.check_if_exists(f"{name}_vtg") - vtg = VideoTimingGenerator(default_video_timings=timings) + vtg = VideoTimingGenerator(default_video_timings=timings if isinstance(timings, str) else timings[1]) vtg = ClockDomainsRenamer(clock_domain)(vtg) setattr(self.submodules, f"{name}_vtg", vtg) # Video Terminal. + timings = timings if isinstance(timings, str) else timings[0] vt = VideoTerminal( hres = int(timings.split("@")[0].split("x")[0]), vres = int(timings.split("@")[0].split("x")[1]), @@ -1728,11 +1729,12 @@ class LiteXSoC(SoC): from litex.soc.cores.video import VideoTimingGenerator, VideoFrameBuffer # Video Timing Generator. - vtg = VideoTimingGenerator(default_video_timings=timings) + vtg = VideoTimingGenerator(default_video_timings=timings if isinstance(timings, str) else timings[1]) vtg = ClockDomainsRenamer(clock_domain)(vtg) setattr(self.submodules, f"{name}_vtg", vtg) # Video FrameBuffer. + timings = timings if isinstance(timings, str) else timings[0] base = self.mem_map.get(name, 0x40c00000) hres = int(timings.split("@")[0].split("x")[0]) vres = int(timings.split("@")[0].split("x")[1])