From 2d23ab7a85cb24e23d5629b457fc6bd0c6b40374 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 1 Apr 2015 22:38:04 +0200 Subject: [PATCH 1/4] soc/sdram: fix do_finalize --- misoclib/soc/sdram.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index d921285a5..a878727ac 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -78,7 +78,7 @@ class SDRAMSoC(SoC): raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width)) def do_finalize(self): - if not self.integrated_ram_size: + if not self.integrated_main_ram_size: if not self._sdram_phy_registered: raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()") SoC.do_finalize(self) From f65c0a3c953e163cbe785c7812e13ccb5b0db337 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 1 Apr 2015 22:45:57 +0200 Subject: [PATCH 2/4] adapt LiteScope to new SoC --- misoclib/tools/litescope/example_designs/make.py | 4 +++- misoclib/tools/litescope/example_designs/targets/simple.py | 7 ++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/misoclib/tools/litescope/example_designs/make.py b/misoclib/tools/litescope/example_designs/make.py index 4cac064c4..593ffd77e 100644 --- a/misoclib/tools/litescope/example_designs/make.py +++ b/misoclib/tools/litescope/example_designs/make.py @@ -72,6 +72,8 @@ if __name__ == "__main__": top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) soc = top_class(platform, **top_kwargs) soc.finalize() + memory_regions = soc.get_memory_regions() + csr_regions = soc.get_csr_regions() # decode actions action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"] @@ -130,7 +132,7 @@ RLE: {} subprocess.call(["rm", "-rf", "build/*"]) if actions["build-csr-csv"]: - csr_csv = cpuif.get_csr_csv(soc.csr_regions) + csr_csv = cpuif.get_csr_csv(csr_regions) write_to_file(args.csr_csv, csr_csv) if actions["build-bitstream"]: diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py index 224539017..fc1db076d 100644 --- a/misoclib/tools/litescope/example_designs/targets/simple.py +++ b/misoclib/tools/litescope/example_designs/targets/simple.py @@ -16,14 +16,15 @@ class LiteScopeSoC(SoC, AutoCSR): csr_map.update(SoC.csr_map) def __init__(self, platform): clk_freq = int((1/(platform.default_clk_period))*1000000000) - self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200) - SoC.__init__(self, platform, clk_freq, self.uart2wb, - with_cpu=False, + SoC.__init__(self, platform, clk_freq, + cpu_type="none", with_csr=True, csr_data_width=32, with_uart=False, with_identifier=True, with_timer=False ) + self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)) + self.add_wb_master(self.cpu_or_bridge.wishbone) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.io = LiteScopeIO(8) From dcdf5df4de22017cfd554d6bdd805b18e3da5242 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 1 Apr 2015 22:50:29 +0200 Subject: [PATCH 3/4] adapt LiteEth to new SoC --- misoclib/com/liteeth/example_designs/make.py | 4 +++- misoclib/com/liteeth/example_designs/targets/base.py | 7 ++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/misoclib/com/liteeth/example_designs/make.py b/misoclib/com/liteeth/example_designs/make.py index dcc8bb4c5..6f504bb21 100644 --- a/misoclib/com/liteeth/example_designs/make.py +++ b/misoclib/com/liteeth/example_designs/make.py @@ -72,6 +72,8 @@ if __name__ == "__main__": top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) soc = top_class(platform, **top_kwargs) soc.finalize() + memory_regions = soc.get_memory_regions() + csr_regions = soc.get_csr_regions() # decode actions action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"] @@ -121,7 +123,7 @@ System Clk: {} MHz subprocess.call(["rm", "-rf", "build/*"]) if actions["build-csr-csv"]: - csr_csv = cpuif.get_csr_csv(soc.csr_regions) + csr_csv = cpuif.get_csr_csv(csr_regions) write_to_file(args.csr_csv, csr_csv) if actions["build-bitstream"]: diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py index 3c2a120f8..f1d95dd72 100644 --- a/misoclib/com/liteeth/example_designs/targets/base.py +++ b/misoclib/com/liteeth/example_designs/targets/base.py @@ -23,14 +23,15 @@ class BaseSoC(SoC, AutoCSR): mac_address=0x10e2d5000000, ip_address="192.168.0.42"): clk_freq = int((1/(platform.default_clk_period))*1000000000) - self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200) - SoC.__init__(self, platform, clk_freq, self.uart2wb, - with_cpu=False, + SoC.__init__(self, platform, clk_freq, + cpu_type="none", with_csr=True, csr_data_width=32, with_uart=False, with_identifier=True, with_timer=False ) + self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)) + self.add_wb_master(self.cpu_or_bridge.wishbone) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # wishbone SRAM (to test Wishbone over UART and Etherbone) From 60124be293f5e8b3c2741d243f67366fd4a9acb6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 1 Apr 2015 22:52:19 +0200 Subject: [PATCH 4/4] adapt LiteSATA to new SoC --- misoclib/mem/litesata/example_designs/make.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/misoclib/mem/litesata/example_designs/make.py b/misoclib/mem/litesata/example_designs/make.py index c8f67b3d2..80452cdfc 100755 --- a/misoclib/mem/litesata/example_designs/make.py +++ b/misoclib/mem/litesata/example_designs/make.py @@ -69,6 +69,8 @@ if __name__ == "__main__": top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) soc = top_class(platform, **top_kwargs) soc.finalize() + memory_regions = soc.get_memory_regions() + csr_regions = soc.get_csr_regions() # decode actions action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"] @@ -124,7 +126,7 @@ BIST: {} subprocess.call(["rm", "-rf", "build/*"]) if actions["build-csr-csv"]: - csr_csv = cpuif.get_csr_csv(soc.get_csr_regions()) + csr_csv = cpuif.get_csr_csv(csr_regions) write_to_file(args.csr_csv, csr_csv) if actions["build-core"]: