From bc667c64568cd32a4c105e540c1f68cf1f8eb28a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 17 Jun 2022 16:04:25 +0200 Subject: [PATCH] interconnect/axi/axi_full/AXIInterface: Add name/bursting parameters. To add compatibility with AXILiteInterface and allow dynamic selection. --- litex/soc/interconnect/axi/axi_full.py | 13 +++++++------ litex/soc/interconnect/axi/axi_lite.py | 6 +++--- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/litex/soc/interconnect/axi/axi_full.py b/litex/soc/interconnect/axi/axi_full.py index 081a4a514..d6740e6fc 100644 --- a/litex/soc/interconnect/axi/axi_full.py +++ b/litex/soc/interconnect/axi/axi_full.py @@ -53,17 +53,18 @@ def r_description(data_width, id_width): ] class AXIInterface: - def __init__(self, data_width=32, address_width=32, id_width=1, clock_domain="sys"): + def __init__(self, data_width=32, address_width=32, id_width=1, clock_domain="sys", name=None, bursting=False): self.data_width = data_width self.address_width = address_width self.id_width = id_width self.clock_domain = clock_domain + self.bursting = bursting # FIXME: Use or add check. - self.aw = stream.Endpoint(ax_description(address_width, id_width)) - self.w = stream.Endpoint(w_description(data_width, id_width)) - self.b = stream.Endpoint(b_description(id_width)) - self.ar = stream.Endpoint(ax_description(address_width, id_width)) - self.r = stream.Endpoint(r_description(data_width, id_width)) + self.aw = stream.Endpoint(ax_description(address_width, id_width), name=name) + self.w = stream.Endpoint(w_description(data_width, id_width), name=name) + self.b = stream.Endpoint(b_description(id_width), name=name) + self.ar = stream.Endpoint(ax_description(address_width, id_width), name=name) + self.r = stream.Endpoint(r_description(data_width, id_width), name=name) def connect_to_pads(self, pads, mode="master"): return connect_to_pads(self, pads, mode, axi_full=True) diff --git a/litex/soc/interconnect/axi/axi_lite.py b/litex/soc/interconnect/axi/axi_lite.py index c83aa1e9d..3fb7a763c 100644 --- a/litex/soc/interconnect/axi/axi_lite.py +++ b/litex/soc/interconnect/axi/axi_lite.py @@ -45,10 +45,10 @@ class AXILiteInterface: raise NotImplementedError("AXI-Lite does not support bursting") self.aw = stream.Endpoint(ax_lite_description(address_width), name=name) - self.w = stream.Endpoint(w_lite_description(data_width), name=name) - self.b = stream.Endpoint(b_lite_description(), name=name) + self.w = stream.Endpoint(w_lite_description(data_width), name=name) + self.b = stream.Endpoint(b_lite_description(), name=name) self.ar = stream.Endpoint(ax_lite_description(address_width), name=name) - self.r = stream.Endpoint(r_lite_description(data_width), name=name) + self.r = stream.Endpoint(r_lite_description(data_width), name=name) def get_ios(self, bus_name="wb"): subsignals = []