From bc8974dad11e2dac4bee66e2e446123ceaf93159 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 24 Mar 2021 17:26:48 +0100 Subject: [PATCH] litex_sim: Switch to soc_core_args/soc_core_argdict. --- litex/tools/litex_sim.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index 921e676e8..fecbb65c3 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -19,7 +19,6 @@ from litex.build.sim.config import SimConfig from litex.soc.integration.common import * from litex.soc.integration.soc_core import * -from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.integration.soc import * from litex.soc.cores.bitbang import * @@ -369,7 +368,7 @@ def generate_gtkw_savefile(builder, vns, trace_fst): def sim_args(parser): builder_args(parser) - soc_sdram_args(parser) + soc_core_args(parser) parser.add_argument("--threads", default=1, help="Set number of threads (default=1)") parser.add_argument("--rom-init", default=None, help="rom_init file") parser.add_argument("--ram-init", default=None, help="ram_init file") @@ -399,7 +398,7 @@ def main(): sim_args(parser) args = parser.parse_args() - soc_kwargs = soc_sdram_argdict(args) + soc_kwargs = soc_core_argdict(args) builder_kwargs = builder_argdict(args) sys_clk_freq = int(1e6)