From c6c743915acb309928dc2f267c8e324694a71feb Mon Sep 17 00:00:00 2001 From: Francis Lam Date: Sun, 14 Jul 2019 12:27:28 -0700 Subject: [PATCH] soc: cores: fix name of EHXPLLL output clock in ECP5PLL --- litex/soc/cores/clock.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index eb44d8498..d5a8f4929 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -476,7 +476,7 @@ class ECP5PLL(Module): p_CLKI_DIV=1, ) for n, (clk, f, p, m) in sorted(self.clkouts.items()): - n_to_l = {0: "P", 1: "S", 2: "OS2"} + n_to_l = {0: "P", 1: "S", 2: "S2"} self.params["p_CLKO{}_ENABLE".format(n_to_l[n])] = "ENABLED" self.params["p_CLKO{}_DIV".format(n_to_l[n])] = config["clko{}_div".format(n)] self.params["p_CLKO{}_FPHASE".format(n_to_l[n])] = 0