From bd74d3933858a12996ccf126d1b5464506d1f616 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 23 Sep 2015 00:35:02 +0800 Subject: [PATCH] misoclib -> misoc --- make.py | 4 +- {misoclib => misoc}/__init__.py | 0 {misoclib => misoc}/com/__init__.py | 0 {misoclib => misoc}/com/gpio.py | 0 {misoclib => misoc}/com/liteethmini/LICENSE | 0 {misoclib => misoc}/com/liteethmini/README | 0 .../com/liteethmini/__init__.py | 0 {misoclib => misoc}/com/liteethmini/common.py | 0 .../com/liteethmini/mac/__init__.py | 6 +- .../com/liteethmini/mac/core/__init__.py | 8 +- .../com/liteethmini/mac/core/crc.py | 2 +- .../com/liteethmini/mac/core/gap.py | 2 +- .../com/liteethmini/mac/core/last_be.py | 2 +- .../com/liteethmini/mac/core/padding.py | 2 +- .../com/liteethmini/mac/core/preamble.py | 2 +- .../com/liteethmini/mac/frontend/__init__.py | 0 .../com/liteethmini/mac/frontend/sram.py | 2 +- .../com/liteethmini/mac/frontend/wishbone.py | 4 +- .../com/liteethmini/phy/__init__.py | 10 +-- .../com/liteethmini/phy/gmii.py | 2 +- .../com/liteethmini/phy/gmii_mii.py | 8 +- .../com/liteethmini/phy/loopback.py | 4 +- .../com/liteethmini/phy/mii.py | 2 +- .../com/liteethmini/phy/s6rgmii.py | 2 +- .../com/liteethmini/phy/sim.py | 2 +- {misoclib => misoc}/com/spi/__init__.py | 0 .../com/spi/test/spi_master_tb.py | 2 +- {misoclib => misoc}/com/uart/__init__.py | 0 {misoclib => misoc}/com/uart/bridge.py | 4 +- {misoclib => misoc}/com/uart/phy/__init__.py | 4 +- {misoclib => misoc}/com/uart/phy/serial.py | 0 {misoclib => misoc}/com/uart/phy/sim.py | 0 .../com/uart/software/__init__.py | 0 {misoclib => misoc}/com/uart/software/reg.py | 0 .../com/uart/software/wishbone.py | 2 +- .../com/uart/test/test_serial_phy.py | 0 {misoclib => misoc}/cpu/__init__.py | 0 {misoclib => misoc}/cpu/identifier.py | 0 {misoclib => misoc}/cpu/lm32.py | 0 {misoclib => misoc}/cpu/mor1kx.py | 0 {misoclib => misoc}/cpu/timer.py | 0 {misoclib => misoc}/mem/__init__.py | 0 {misoclib => misoc}/mem/flash/__init__.py | 0 {misoclib => misoc}/mem/flash/norflash16.py | 0 {misoclib => misoc}/mem/flash/spiflash.py | 0 {misoclib => misoc}/mem/sdram/__init__.py | 0 .../mem/sdram/core/__init__.py | 6 +- .../mem/sdram/core/lasmibus.py | 0 .../mem/sdram/core/lasmicon/__init__.py | 10 +-- .../mem/sdram/core/lasmicon/bankmachine.py | 2 +- .../mem/sdram/core/lasmicon/multiplexer.py | 2 +- .../mem/sdram/core/lasmicon/perf.py | 0 .../mem/sdram/core/lasmicon/refresher.py | 2 +- .../mem/sdram/core/lasmixbar.py | 2 +- .../mem/sdram/core/minicon/__init__.py | 2 +- .../mem/sdram/frontend/__init__.py | 0 .../mem/sdram/frontend/dma_lasmi.py | 0 .../mem/sdram/frontend/memtest.py | 2 +- .../mem/sdram/frontend/wishbone2lasmi.py | 0 {misoclib => misoc}/mem/sdram/module.py | 2 +- {misoclib => misoc}/mem/sdram/phy/__init__.py | 0 {misoclib => misoc}/mem/sdram/phy/dfi.py | 0 {misoclib => misoc}/mem/sdram/phy/dfii.py | 2 +- .../mem/sdram/phy/gensdrphy.py | 4 +- .../mem/sdram/phy/initsequence.py | 0 {misoclib => misoc}/mem/sdram/phy/k7ddrphy.py | 4 +- {misoclib => misoc}/mem/sdram/phy/s6ddrphy.py | 4 +- {misoclib => misoc}/mem/sdram/phy/simphy.py | 4 +- .../sdram/test/abstract_transactions_lasmi.py | 2 +- .../mem/sdram/test/bankmachine_tb.py | 4 +- {misoclib => misoc}/mem/sdram/test/common.py | 2 +- .../mem/sdram/test/lasmicon_df_tb.py | 6 +- .../mem/sdram/test/lasmicon_tb.py | 4 +- .../mem/sdram/test/lasmicon_wb.py | 6 +- .../mem/sdram/test/minicon_tb.py | 6 +- .../mem/sdram/test/refresher.py | 2 +- {misoclib => misoc}/mxcrg.v | 0 {misoclib => misoc}/soc/__init__.py | 8 +- {misoclib => misoc}/soc/cpuif.py | 0 {misoclib => misoc}/soc/sdram.py | 10 +-- {misoclib => misoc}/tools/__init__.py | 0 {misoclib => misoc}/tools/wishbone.py | 0 {misoclib => misoc}/video/__init__.py | 0 .../video/dvisampler/__init__.py | 18 ++--- .../video/dvisampler/analysis.py | 2 +- .../video/dvisampler/chansync.py | 2 +- .../video/dvisampler/charsync.py | 2 +- .../video/dvisampler/clocking.py | 0 .../video/dvisampler/common.py | 0 .../video/dvisampler/datacapture.py | 0 {misoclib => misoc}/video/dvisampler/debug.py | 8 +- .../video/dvisampler/decoding.py | 2 +- {misoclib => misoc}/video/dvisampler/dma.py | 2 +- {misoclib => misoc}/video/dvisampler/edid.py | 0 {misoclib => misoc}/video/dvisampler/wer.py | 2 +- .../video/framebuffer/__init__.py | 6 +- {misoclib => misoc}/video/framebuffer/dvi.py | 0 .../video/framebuffer/format.py | 0 {misoclib => misoc}/video/framebuffer/phy.py | 4 +- setup.py | 76 +++++++++---------- software/common.mak | 2 +- targets/de0nano.py | 8 +- targets/kc705.py | 16 ++-- targets/minispartan6.py | 8 +- targets/mlabs_video.py | 22 +++--- targets/pipistrello.py | 10 +-- targets/ppro.py | 10 +-- targets/simple.py | 6 +- targets/versa.py | 2 +- 109 files changed, 191 insertions(+), 191 deletions(-) rename {misoclib => misoc}/__init__.py (100%) rename {misoclib => misoc}/com/__init__.py (100%) rename {misoclib => misoc}/com/gpio.py (100%) rename {misoclib => misoc}/com/liteethmini/LICENSE (100%) rename {misoclib => misoc}/com/liteethmini/README (100%) rename {misoclib => misoc}/com/liteethmini/__init__.py (100%) rename {misoclib => misoc}/com/liteethmini/common.py (100%) rename {misoclib => misoc}/com/liteethmini/mac/__init__.py (78%) rename {misoclib => misoc}/com/liteethmini/mac/core/__init__.py (94%) rename {misoclib => misoc}/com/liteethmini/mac/core/crc.py (99%) rename {misoclib => misoc}/com/liteethmini/mac/core/gap.py (94%) rename {misoclib => misoc}/com/liteethmini/mac/core/last_be.py (96%) rename {misoclib => misoc}/com/liteethmini/mac/core/padding.py (97%) rename {misoclib => misoc}/com/liteethmini/mac/core/preamble.py (98%) rename {misoclib => misoc}/com/liteethmini/mac/frontend/__init__.py (100%) rename {misoclib => misoc}/com/liteethmini/mac/frontend/sram.py (99%) rename {misoclib => misoc}/com/liteethmini/mac/frontend/wishbone.py (93%) rename {misoclib => misoc}/com/liteethmini/phy/__init__.py (73%) rename {misoclib => misoc}/com/liteethmini/phy/gmii.py (98%) rename {misoclib => misoc}/com/liteethmini/phy/gmii_mii.py (94%) rename {misoclib => misoc}/com/liteethmini/phy/loopback.py (89%) rename {misoclib => misoc}/com/liteethmini/phy/mii.py (98%) rename {misoclib => misoc}/com/liteethmini/phy/s6rgmii.py (99%) rename {misoclib => misoc}/com/liteethmini/phy/sim.py (97%) rename {misoclib => misoc}/com/spi/__init__.py (100%) rename {misoclib => misoc}/com/spi/test/spi_master_tb.py (98%) rename {misoclib => misoc}/com/uart/__init__.py (100%) rename {misoclib => misoc}/com/uart/bridge.py (70%) rename {misoclib => misoc}/com/uart/phy/__init__.py (62%) rename {misoclib => misoc}/com/uart/phy/serial.py (100%) rename {misoclib => misoc}/com/uart/phy/sim.py (100%) rename {misoclib => misoc}/com/uart/software/__init__.py (100%) rename {misoclib => misoc}/com/uart/software/reg.py (100%) rename {misoclib => misoc}/com/uart/software/wishbone.py (98%) rename {misoclib => misoc}/com/uart/test/test_serial_phy.py (100%) rename {misoclib => misoc}/cpu/__init__.py (100%) rename {misoclib => misoc}/cpu/identifier.py (100%) rename {misoclib => misoc}/cpu/lm32.py (100%) rename {misoclib => misoc}/cpu/mor1kx.py (100%) rename {misoclib => misoc}/cpu/timer.py (100%) rename {misoclib => misoc}/mem/__init__.py (100%) rename {misoclib => misoc}/mem/flash/__init__.py (100%) rename {misoclib => misoc}/mem/flash/norflash16.py (100%) rename {misoclib => misoc}/mem/flash/spiflash.py (100%) rename {misoclib => misoc}/mem/sdram/__init__.py (100%) rename {misoclib => misoc}/mem/sdram/core/__init__.py (92%) rename {misoclib => misoc}/mem/sdram/core/lasmibus.py (100%) rename {misoclib => misoc}/mem/sdram/core/lasmicon/__init__.py (90%) rename {misoclib => misoc}/mem/sdram/core/lasmicon/bankmachine.py (98%) rename {misoclib => misoc}/mem/sdram/core/lasmicon/multiplexer.py (99%) rename {misoclib => misoc}/mem/sdram/core/lasmicon/perf.py (100%) rename {misoclib => misoc}/mem/sdram/core/lasmicon/refresher.py (97%) rename {misoclib => misoc}/mem/sdram/core/lasmixbar.py (99%) rename {misoclib => misoc}/mem/sdram/core/minicon/__init__.py (99%) rename {misoclib => misoc}/mem/sdram/frontend/__init__.py (100%) rename {misoclib => misoc}/mem/sdram/frontend/dma_lasmi.py (100%) rename {misoclib => misoc}/mem/sdram/frontend/memtest.py (98%) rename {misoclib => misoc}/mem/sdram/frontend/wishbone2lasmi.py (100%) rename {misoclib => misoc}/mem/sdram/module.py (99%) rename {misoclib => misoc}/mem/sdram/phy/__init__.py (100%) rename {misoclib => misoc}/mem/sdram/phy/dfi.py (100%) rename {misoclib => misoc}/mem/sdram/phy/dfii.py (98%) rename {misoclib => misoc}/mem/sdram/phy/gensdrphy.py (97%) rename {misoclib => misoc}/mem/sdram/phy/initsequence.py (100%) rename {misoclib => misoc}/mem/sdram/phy/k7ddrphy.py (99%) rename {misoclib => misoc}/mem/sdram/phy/s6ddrphy.py (99%) rename {misoclib => misoc}/mem/sdram/phy/simphy.py (98%) rename {misoclib => misoc}/mem/sdram/test/abstract_transactions_lasmi.py (96%) rename {misoclib => misoc}/mem/sdram/test/bankmachine_tb.py (92%) rename {misoclib => misoc}/mem/sdram/test/common.py (98%) rename {misoclib => misoc}/mem/sdram/test/lasmicon_df_tb.py (90%) rename {misoclib => misoc}/mem/sdram/test/lasmicon_tb.py (92%) rename {misoclib => misoc}/mem/sdram/test/lasmicon_wb.py (89%) rename {misoclib => misoc}/mem/sdram/test/minicon_tb.py (97%) rename {misoclib => misoc}/mem/sdram/test/refresher.py (95%) rename {misoclib => misoc}/mxcrg.v (100%) rename {misoclib => misoc}/soc/__init__.py (98%) rename {misoclib => misoc}/soc/cpuif.py (100%) rename {misoclib => misoc}/soc/sdram.py (95%) rename {misoclib => misoc}/tools/__init__.py (100%) rename {misoclib => misoc}/tools/wishbone.py (100%) rename {misoclib => misoc}/video/__init__.py (100%) rename {misoclib => misoc}/video/dvisampler/__init__.py (83%) rename {misoclib => misoc}/video/dvisampler/analysis.py (99%) rename {misoclib => misoc}/video/dvisampler/chansync.py (98%) rename {misoclib => misoc}/video/dvisampler/charsync.py (96%) rename {misoclib => misoc}/video/dvisampler/clocking.py (100%) rename {misoclib => misoc}/video/dvisampler/common.py (100%) rename {misoclib => misoc}/video/dvisampler/datacapture.py (100%) rename {misoclib => misoc}/video/dvisampler/debug.py (88%) rename {misoclib => misoc}/video/dvisampler/decoding.py (90%) rename {misoclib => misoc}/video/dvisampler/dma.py (99%) rename {misoclib => misoc}/video/dvisampler/edid.py (100%) rename {misoclib => misoc}/video/dvisampler/wer.py (97%) rename {misoclib => misoc}/video/framebuffer/__init__.py (85%) rename {misoclib => misoc}/video/framebuffer/dvi.py (100%) rename {misoclib => misoc}/video/framebuffer/format.py (100%) rename {misoclib => misoc}/video/framebuffer/phy.py (98%) diff --git a/make.py b/make.py index 2d1c51b3f..28b372234 100755 --- a/make.py +++ b/make.py @@ -11,8 +11,8 @@ from mibuild.tools import write_to_file from migen.util.misc import autotype from migen.fhdl import simplify -from misoclib.soc import cpuif -from misoclib.mem.sdram.phy import initsequence +from misoc.soc import cpuif +from misoc.mem.sdram.phy import initsequence from misoc_import import misoc_import diff --git a/misoclib/__init__.py b/misoc/__init__.py similarity index 100% rename from misoclib/__init__.py rename to misoc/__init__.py diff --git a/misoclib/com/__init__.py b/misoc/com/__init__.py similarity index 100% rename from misoclib/com/__init__.py rename to misoc/com/__init__.py diff --git a/misoclib/com/gpio.py b/misoc/com/gpio.py similarity index 100% rename from misoclib/com/gpio.py rename to misoc/com/gpio.py diff --git a/misoclib/com/liteethmini/LICENSE b/misoc/com/liteethmini/LICENSE similarity index 100% rename from misoclib/com/liteethmini/LICENSE rename to misoc/com/liteethmini/LICENSE diff --git a/misoclib/com/liteethmini/README b/misoc/com/liteethmini/README similarity index 100% rename from misoclib/com/liteethmini/README rename to misoc/com/liteethmini/README diff --git a/misoclib/com/liteethmini/__init__.py b/misoc/com/liteethmini/__init__.py similarity index 100% rename from misoclib/com/liteethmini/__init__.py rename to misoc/com/liteethmini/__init__.py diff --git a/misoclib/com/liteethmini/common.py b/misoc/com/liteethmini/common.py similarity index 100% rename from misoclib/com/liteethmini/common.py rename to misoc/com/liteethmini/common.py diff --git a/misoclib/com/liteethmini/mac/__init__.py b/misoc/com/liteethmini/mac/__init__.py similarity index 78% rename from misoclib/com/liteethmini/mac/__init__.py rename to misoc/com/liteethmini/mac/__init__.py index 958f84a8f..6844c420d 100644 --- a/misoclib/com/liteethmini/mac/__init__.py +++ b/misoc/com/liteethmini/mac/__init__.py @@ -1,6 +1,6 @@ -from misoclib.com.liteethmini.common import * -from misoclib.com.liteethmini.mac.core import LiteEthMACCore -from misoclib.com.liteethmini.mac.frontend.wishbone import LiteEthMACWishboneInterface +from misoc.com.liteethmini.common import * +from misoc.com.liteethmini.mac.core import LiteEthMACCore +from misoc.com.liteethmini.mac.frontend.wishbone import LiteEthMACWishboneInterface class LiteEthMAC(Module, AutoCSR): diff --git a/misoclib/com/liteethmini/mac/core/__init__.py b/misoc/com/liteethmini/mac/core/__init__.py similarity index 94% rename from misoclib/com/liteethmini/mac/core/__init__.py rename to misoc/com/liteethmini/mac/core/__init__.py index 99c743627..2551f5ebb 100644 --- a/misoclib/com/liteethmini/mac/core/__init__.py +++ b/misoc/com/liteethmini/mac/core/__init__.py @@ -1,7 +1,7 @@ -from misoclib.com.liteethmini.common import * -from misoclib.com.liteethmini.mac.core import gap, preamble, crc, padding, last_be -from misoclib.com.liteethmini.phy.sim import LiteEthPHYSim -from misoclib.com.liteethmini.phy.mii import LiteEthPHYMII +from misoc.com.liteethmini.common import * +from misoc.com.liteethmini.mac.core import gap, preamble, crc, padding, last_be +from misoc.com.liteethmini.phy.sim import LiteEthPHYSim +from misoc.com.liteethmini.phy.mii import LiteEthPHYMII class LiteEthMACCore(Module, AutoCSR): diff --git a/misoclib/com/liteethmini/mac/core/crc.py b/misoc/com/liteethmini/mac/core/crc.py similarity index 99% rename from misoclib/com/liteethmini/mac/core/crc.py rename to misoc/com/liteethmini/mac/core/crc.py index e06b92882..01b88f7e6 100644 --- a/misoclib/com/liteethmini/mac/core/crc.py +++ b/misoc/com/liteethmini/mac/core/crc.py @@ -1,4 +1,4 @@ -from misoclib.com.liteethmini.common import * +from misoc.com.liteethmini.common import * class LiteEthMACCRCEngine(Module): diff --git a/misoclib/com/liteethmini/mac/core/gap.py b/misoc/com/liteethmini/mac/core/gap.py similarity index 94% rename from misoclib/com/liteethmini/mac/core/gap.py rename to misoc/com/liteethmini/mac/core/gap.py index fa95d1892..ce4ad1ba7 100644 --- a/misoclib/com/liteethmini/mac/core/gap.py +++ b/misoc/com/liteethmini/mac/core/gap.py @@ -1,4 +1,4 @@ -from misoclib.com.liteethmini.common import * +from misoc.com.liteethmini.common import * class LiteEthMACGap(Module): def __init__(self, dw, ack_on_gap=False): diff --git a/misoclib/com/liteethmini/mac/core/last_be.py b/misoc/com/liteethmini/mac/core/last_be.py similarity index 96% rename from misoclib/com/liteethmini/mac/core/last_be.py rename to misoc/com/liteethmini/mac/core/last_be.py index e469008d0..14d8a3088 100644 --- a/misoclib/com/liteethmini/mac/core/last_be.py +++ b/misoc/com/liteethmini/mac/core/last_be.py @@ -1,4 +1,4 @@ -from misoclib.com.liteethmini.common import * +from misoc.com.liteethmini.common import * class LiteEthMACTXLastBE(Module): diff --git a/misoclib/com/liteethmini/mac/core/padding.py b/misoc/com/liteethmini/mac/core/padding.py similarity index 97% rename from misoclib/com/liteethmini/mac/core/padding.py rename to misoc/com/liteethmini/mac/core/padding.py index fbd878335..fa4aa927e 100644 --- a/misoclib/com/liteethmini/mac/core/padding.py +++ b/misoc/com/liteethmini/mac/core/padding.py @@ -1,4 +1,4 @@ -from misoclib.com.liteethmini.common import * +from misoc.com.liteethmini.common import * class LiteEthMACPaddingInserter(Module): diff --git a/misoclib/com/liteethmini/mac/core/preamble.py b/misoc/com/liteethmini/mac/core/preamble.py similarity index 98% rename from misoclib/com/liteethmini/mac/core/preamble.py rename to misoc/com/liteethmini/mac/core/preamble.py index 445a07388..52078f906 100644 --- a/misoclib/com/liteethmini/mac/core/preamble.py +++ b/misoc/com/liteethmini/mac/core/preamble.py @@ -1,4 +1,4 @@ -from misoclib.com.liteethmini.common import * +from misoc.com.liteethmini.common import * class LiteEthMACPreambleInserter(Module): diff --git a/misoclib/com/liteethmini/mac/frontend/__init__.py b/misoc/com/liteethmini/mac/frontend/__init__.py similarity index 100% rename from misoclib/com/liteethmini/mac/frontend/__init__.py rename to misoc/com/liteethmini/mac/frontend/__init__.py diff --git a/misoclib/com/liteethmini/mac/frontend/sram.py b/misoc/com/liteethmini/mac/frontend/sram.py similarity index 99% rename from misoclib/com/liteethmini/mac/frontend/sram.py rename to misoc/com/liteethmini/mac/frontend/sram.py index b5e91a333..1495e08e1 100644 --- a/misoclib/com/liteethmini/mac/frontend/sram.py +++ b/misoc/com/liteethmini/mac/frontend/sram.py @@ -1,4 +1,4 @@ -from misoclib.com.liteethmini.common import * +from misoc.com.liteethmini.common import * from migen.bank.description import * from migen.bank.eventmanager import * diff --git a/misoclib/com/liteethmini/mac/frontend/wishbone.py b/misoc/com/liteethmini/mac/frontend/wishbone.py similarity index 93% rename from misoclib/com/liteethmini/mac/frontend/wishbone.py rename to misoc/com/liteethmini/mac/frontend/wishbone.py index 896230898..e45f744ef 100644 --- a/misoclib/com/liteethmini/mac/frontend/wishbone.py +++ b/misoc/com/liteethmini/mac/frontend/wishbone.py @@ -1,5 +1,5 @@ -from misoclib.com.liteethmini.common import * -from misoclib.com.liteethmini.mac.frontend import sram +from misoc.com.liteethmini.common import * +from misoc.com.liteethmini.mac.frontend import sram from migen.bus import wishbone from migen.fhdl.simplify import FullMemoryWE diff --git a/misoclib/com/liteethmini/phy/__init__.py b/misoc/com/liteethmini/phy/__init__.py similarity index 73% rename from misoclib/com/liteethmini/phy/__init__.py rename to misoc/com/liteethmini/phy/__init__.py index f3a15b8e7..c17124d1e 100644 --- a/misoclib/com/liteethmini/phy/__init__.py +++ b/misoc/com/liteethmini/phy/__init__.py @@ -1,27 +1,27 @@ -from misoclib.com.liteethmini.common import * +from misoc.com.liteethmini.common import * def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs): # Autodetect PHY if hasattr(pads, "source_stb"): # This is a simulation PHY - from misoclib.com.liteethmini.phy.sim import LiteEthPHYSim + from misoc.com.liteethmini.phy.sim import LiteEthPHYSim return LiteEthPHYSim(pads) elif hasattr(clock_pads, "gtx") and flen(pads.tx_data) == 8: if hasattr(clock_pads, "tx"): # This is a 10/100/1G PHY - from misoclib.com.liteethmini.phy.gmii_mii import LiteEthPHYGMIIMII + from misoc.com.liteethmini.phy.gmii_mii import LiteEthPHYGMIIMII return LiteEthPHYGMIIMII(clock_pads, pads, clk_freq=clk_freq, **kwargs) else: # This is a pure 1G PHY - from misoclib.com.liteethmini.phy.gmii import LiteEthPHYGMII + from misoc.com.liteethmini.phy.gmii import LiteEthPHYGMII return LiteEthPHYGMII(clock_pads, pads, **kwargs) elif hasattr(pads, "rx_ctl"): # This is a 10/100/1G RGMII PHY raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation") elif flen(pads.tx_data) == 4: # This is a MII PHY - from misoclib.com.liteethmini.phy.mii import LiteEthPHYMII + from misoc.com.liteethmini.phy.mii import LiteEthPHYMII return LiteEthPHYMII(clock_pads, pads, **kwargs) else: raise ValueError("Unable to autodetect PHY from platform file, use direct instantiation") diff --git a/misoclib/com/liteethmini/phy/gmii.py b/misoc/com/liteethmini/phy/gmii.py similarity index 98% rename from misoclib/com/liteethmini/phy/gmii.py rename to misoc/com/liteethmini/phy/gmii.py index db9c287fd..24f4dc8f3 100644 --- a/misoclib/com/liteethmini/phy/gmii.py +++ b/misoc/com/liteethmini/phy/gmii.py @@ -1,6 +1,6 @@ from migen.genlib.io import DDROutput -from misoclib.com.liteethmini.common import * +from misoc.com.liteethmini.common import * class LiteEthPHYGMIITX(Module): diff --git a/misoclib/com/liteethmini/phy/gmii_mii.py b/misoc/com/liteethmini/phy/gmii_mii.py similarity index 94% rename from misoclib/com/liteethmini/phy/gmii_mii.py rename to misoc/com/liteethmini/phy/gmii_mii.py index 2d92d821a..8ed4741ea 100644 --- a/misoclib/com/liteethmini/phy/gmii_mii.py +++ b/misoc/com/liteethmini/phy/gmii_mii.py @@ -2,11 +2,11 @@ from migen.genlib.io import DDROutput from migen.flow.plumbing import Multiplexer, Demultiplexer from migen.genlib.cdc import PulseSynchronizer -from misoclib.com.liteethmini.common import * +from misoc.com.liteethmini.common import * -from misoclib.com.liteethmini.phy.gmii import LiteEthPHYGMIICRG -from misoclib.com.liteethmini.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX -from misoclib.com.liteethmini.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX +from misoc.com.liteethmini.phy.gmii import LiteEthPHYGMIICRG +from misoc.com.liteethmini.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX +from misoc.com.liteethmini.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX modes = { "GMII": 0, diff --git a/misoclib/com/liteethmini/phy/loopback.py b/misoc/com/liteethmini/phy/loopback.py similarity index 89% rename from misoclib/com/liteethmini/phy/loopback.py rename to misoc/com/liteethmini/phy/loopback.py index 7e4863cca..c9e5cf1c1 100644 --- a/misoclib/com/liteethmini/phy/loopback.py +++ b/misoc/com/liteethmini/phy/loopback.py @@ -1,5 +1,5 @@ -from misoclib.com.liteethmini.common import * -from misoclib.com.liteethmini.generic import * +from misoc.com.liteethmini.common import * +from misoc.com.liteethmini.generic import * class LiteEthPHYLoopbackCRG(Module, AutoCSR): diff --git a/misoclib/com/liteethmini/phy/mii.py b/misoc/com/liteethmini/phy/mii.py similarity index 98% rename from misoclib/com/liteethmini/phy/mii.py rename to misoc/com/liteethmini/phy/mii.py index 53a20a79c..695652464 100644 --- a/misoclib/com/liteethmini/phy/mii.py +++ b/misoc/com/liteethmini/phy/mii.py @@ -1,4 +1,4 @@ -from misoclib.com.liteethmini.common import * +from misoc.com.liteethmini.common import * def converter_description(dw): diff --git a/misoclib/com/liteethmini/phy/s6rgmii.py b/misoc/com/liteethmini/phy/s6rgmii.py similarity index 99% rename from misoclib/com/liteethmini/phy/s6rgmii.py rename to misoc/com/liteethmini/phy/s6rgmii.py index 31656d24e..8f7da75f5 100644 --- a/misoclib/com/liteethmini/phy/s6rgmii.py +++ b/misoc/com/liteethmini/phy/s6rgmii.py @@ -4,7 +4,7 @@ from migen.genlib.io import DDROutput from migen.genlib.misc import WaitTimer from migen.genlib.fsm import FSM, NextState -from misoclib.com.liteethmini.common import * +from misoc.com.liteethmini.common import * class LiteEthPHYRGMIITX(Module): diff --git a/misoclib/com/liteethmini/phy/sim.py b/misoc/com/liteethmini/phy/sim.py similarity index 97% rename from misoclib/com/liteethmini/phy/sim.py rename to misoc/com/liteethmini/phy/sim.py index 8c2905255..d6d1778dd 100644 --- a/misoclib/com/liteethmini/phy/sim.py +++ b/misoc/com/liteethmini/phy/sim.py @@ -1,6 +1,6 @@ import os -from misoclib.com.liteethmini.common import * +from misoc.com.liteethmini.common import * class LiteEthPHYSimCRG(Module, AutoCSR): diff --git a/misoclib/com/spi/__init__.py b/misoc/com/spi/__init__.py similarity index 100% rename from misoclib/com/spi/__init__.py rename to misoc/com/spi/__init__.py diff --git a/misoclib/com/spi/test/spi_master_tb.py b/misoc/com/spi/test/spi_master_tb.py similarity index 98% rename from misoclib/com/spi/test/spi_master_tb.py rename to misoc/com/spi/test/spi_master_tb.py index f20aa19f2..51a30c66b 100644 --- a/misoclib/com/spi/test/spi_master_tb.py +++ b/misoc/com/spi/test/spi_master_tb.py @@ -2,7 +2,7 @@ from migen.fhdl.std import * from migen.genlib.record import * from migen.sim.generic import run_simulation -from misoclib.com.spi import SPIMaster +from misoc.com.spi import SPIMaster class SPISlave(Module): diff --git a/misoclib/com/uart/__init__.py b/misoc/com/uart/__init__.py similarity index 100% rename from misoclib/com/uart/__init__.py rename to misoc/com/uart/__init__.py diff --git a/misoclib/com/uart/bridge.py b/misoc/com/uart/bridge.py similarity index 70% rename from misoclib/com/uart/bridge.py rename to misoc/com/uart/bridge.py index fc0d292ed..6917f3555 100644 --- a/misoclib/com/uart/bridge.py +++ b/misoc/com/uart/bridge.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * -from misoclib.tools.wishbone import WishboneStreamingBridge -from misoclib.com.uart.phy.serial import UARTPHYSerial +from misoc.tools.wishbone import WishboneStreamingBridge +from misoc.com.uart.phy.serial import UARTPHYSerial class UARTWishboneBridge(WishboneStreamingBridge): def __init__(self, pads, clk_freq, baudrate=115200): diff --git a/misoclib/com/uart/phy/__init__.py b/misoc/com/uart/phy/__init__.py similarity index 62% rename from misoclib/com/uart/phy/__init__.py rename to misoc/com/uart/phy/__init__.py index c6506c81f..76ebd80bc 100644 --- a/misoclib/com/uart/phy/__init__.py +++ b/misoc/com/uart/phy/__init__.py @@ -1,8 +1,8 @@ def UARTPHY(pads, *args, **kwargs): # Autodetect PHY if hasattr(pads, "source_stb"): - from misoclib.com.uart.phy.sim import UARTPHYSim + from misoc.com.uart.phy.sim import UARTPHYSim return UARTPHYSim(pads, *args, **kwargs) else: - from misoclib.com.uart.phy.serial import UARTPHYSerial + from misoc.com.uart.phy.serial import UARTPHYSerial return UARTPHYSerial(pads, *args, **kwargs) diff --git a/misoclib/com/uart/phy/serial.py b/misoc/com/uart/phy/serial.py similarity index 100% rename from misoclib/com/uart/phy/serial.py rename to misoc/com/uart/phy/serial.py diff --git a/misoclib/com/uart/phy/sim.py b/misoc/com/uart/phy/sim.py similarity index 100% rename from misoclib/com/uart/phy/sim.py rename to misoc/com/uart/phy/sim.py diff --git a/misoclib/com/uart/software/__init__.py b/misoc/com/uart/software/__init__.py similarity index 100% rename from misoclib/com/uart/software/__init__.py rename to misoc/com/uart/software/__init__.py diff --git a/misoclib/com/uart/software/reg.py b/misoc/com/uart/software/reg.py similarity index 100% rename from misoclib/com/uart/software/reg.py rename to misoc/com/uart/software/reg.py diff --git a/misoclib/com/uart/software/wishbone.py b/misoc/com/uart/software/wishbone.py similarity index 98% rename from misoclib/com/uart/software/wishbone.py rename to misoc/com/uart/software/wishbone.py index d581dbbf4..608ccf2c3 100644 --- a/misoclib/com/uart/software/wishbone.py +++ b/misoc/com/uart/software/wishbone.py @@ -1,6 +1,6 @@ import serial from struct import * -from misoclib.com.uart.software.reg import * +from misoc.com.uart.software.reg import * def write_b(uart, data): diff --git a/misoclib/com/uart/test/test_serial_phy.py b/misoc/com/uart/test/test_serial_phy.py similarity index 100% rename from misoclib/com/uart/test/test_serial_phy.py rename to misoc/com/uart/test/test_serial_phy.py diff --git a/misoclib/cpu/__init__.py b/misoc/cpu/__init__.py similarity index 100% rename from misoclib/cpu/__init__.py rename to misoc/cpu/__init__.py diff --git a/misoclib/cpu/identifier.py b/misoc/cpu/identifier.py similarity index 100% rename from misoclib/cpu/identifier.py rename to misoc/cpu/identifier.py diff --git a/misoclib/cpu/lm32.py b/misoc/cpu/lm32.py similarity index 100% rename from misoclib/cpu/lm32.py rename to misoc/cpu/lm32.py diff --git a/misoclib/cpu/mor1kx.py b/misoc/cpu/mor1kx.py similarity index 100% rename from misoclib/cpu/mor1kx.py rename to misoc/cpu/mor1kx.py diff --git a/misoclib/cpu/timer.py b/misoc/cpu/timer.py similarity index 100% rename from misoclib/cpu/timer.py rename to misoc/cpu/timer.py diff --git a/misoclib/mem/__init__.py b/misoc/mem/__init__.py similarity index 100% rename from misoclib/mem/__init__.py rename to misoc/mem/__init__.py diff --git a/misoclib/mem/flash/__init__.py b/misoc/mem/flash/__init__.py similarity index 100% rename from misoclib/mem/flash/__init__.py rename to misoc/mem/flash/__init__.py diff --git a/misoclib/mem/flash/norflash16.py b/misoc/mem/flash/norflash16.py similarity index 100% rename from misoclib/mem/flash/norflash16.py rename to misoc/mem/flash/norflash16.py diff --git a/misoclib/mem/flash/spiflash.py b/misoc/mem/flash/spiflash.py similarity index 100% rename from misoclib/mem/flash/spiflash.py rename to misoc/mem/flash/spiflash.py diff --git a/misoclib/mem/sdram/__init__.py b/misoc/mem/sdram/__init__.py similarity index 100% rename from misoclib/mem/sdram/__init__.py rename to misoc/mem/sdram/__init__.py diff --git a/misoclib/mem/sdram/core/__init__.py b/misoc/mem/sdram/core/__init__.py similarity index 92% rename from misoclib/mem/sdram/core/__init__.py rename to misoc/mem/sdram/core/__init__.py index 1892f8181..287bdf57d 100644 --- a/misoclib/mem/sdram/core/__init__.py +++ b/misoc/mem/sdram/core/__init__.py @@ -2,9 +2,9 @@ from migen.fhdl.std import * from migen.genlib.record import * from migen.bank.description import * -from misoclib.mem.sdram.phy import dfii -from misoclib.mem.sdram.core import minicon, lasmicon -from misoclib.mem.sdram.core import lasmixbar +from misoc.mem.sdram.phy import dfii +from misoc.mem.sdram.core import minicon, lasmicon +from misoc.mem.sdram.core import lasmixbar class SDRAMCore(Module, AutoCSR): diff --git a/misoclib/mem/sdram/core/lasmibus.py b/misoc/mem/sdram/core/lasmibus.py similarity index 100% rename from misoclib/mem/sdram/core/lasmibus.py rename to misoc/mem/sdram/core/lasmibus.py diff --git a/misoclib/mem/sdram/core/lasmicon/__init__.py b/misoc/mem/sdram/core/lasmicon/__init__.py similarity index 90% rename from misoclib/mem/sdram/core/lasmicon/__init__.py rename to misoc/mem/sdram/core/lasmicon/__init__.py index 5614cece7..170e085ae 100644 --- a/misoclib/mem/sdram/core/lasmicon/__init__.py +++ b/misoc/mem/sdram/core/lasmicon/__init__.py @@ -1,10 +1,10 @@ from migen.fhdl.std import * -from misoclib.mem.sdram.phy import dfi -from misoclib.mem.sdram.core import lasmibus -from misoclib.mem.sdram.core.lasmicon.refresher import * -from misoclib.mem.sdram.core.lasmicon.bankmachine import * -from misoclib.mem.sdram.core.lasmicon.multiplexer import * +from misoc.mem.sdram.phy import dfi +from misoc.mem.sdram.core import lasmibus +from misoc.mem.sdram.core.lasmicon.refresher import * +from misoc.mem.sdram.core.lasmicon.bankmachine import * +from misoc.mem.sdram.core.lasmicon.multiplexer import * class LASMIconSettings: diff --git a/misoclib/mem/sdram/core/lasmicon/bankmachine.py b/misoc/mem/sdram/core/lasmicon/bankmachine.py similarity index 98% rename from misoclib/mem/sdram/core/lasmicon/bankmachine.py rename to misoc/mem/sdram/core/lasmicon/bankmachine.py index cd5bcab50..1f58dd435 100644 --- a/misoclib/mem/sdram/core/lasmicon/bankmachine.py +++ b/misoc/mem/sdram/core/lasmicon/bankmachine.py @@ -4,7 +4,7 @@ from migen.genlib.fsm import FSM, NextState from migen.genlib.misc import optree from migen.genlib.fifo import SyncFIFO -from misoclib.mem.sdram.core.lasmicon.multiplexer import * +from misoc.mem.sdram.core.lasmicon.multiplexer import * class _AddressSlicer: diff --git a/misoclib/mem/sdram/core/lasmicon/multiplexer.py b/misoc/mem/sdram/core/lasmicon/multiplexer.py similarity index 99% rename from misoclib/mem/sdram/core/lasmicon/multiplexer.py rename to misoc/mem/sdram/core/lasmicon/multiplexer.py index ca9b96235..d03d4dfda 100644 --- a/misoclib/mem/sdram/core/lasmicon/multiplexer.py +++ b/misoc/mem/sdram/core/lasmicon/multiplexer.py @@ -4,7 +4,7 @@ from migen.genlib.misc import optree from migen.genlib.fsm import FSM, NextState from migen.bank.description import AutoCSR -from misoclib.mem.sdram.core.lasmicon.perf import Bandwidth +from misoc.mem.sdram.core.lasmicon.perf import Bandwidth class CommandRequest: diff --git a/misoclib/mem/sdram/core/lasmicon/perf.py b/misoc/mem/sdram/core/lasmicon/perf.py similarity index 100% rename from misoclib/mem/sdram/core/lasmicon/perf.py rename to misoc/mem/sdram/core/lasmicon/perf.py diff --git a/misoclib/mem/sdram/core/lasmicon/refresher.py b/misoc/mem/sdram/core/lasmicon/refresher.py similarity index 97% rename from misoclib/mem/sdram/core/lasmicon/refresher.py rename to misoc/mem/sdram/core/lasmicon/refresher.py index 007309a9b..12aeefc4e 100644 --- a/misoclib/mem/sdram/core/lasmicon/refresher.py +++ b/misoc/mem/sdram/core/lasmicon/refresher.py @@ -2,7 +2,7 @@ from migen.fhdl.std import * from migen.genlib.misc import timeline from migen.genlib.fsm import FSM -from misoclib.mem.sdram.core.lasmicon.multiplexer import * +from misoc.mem.sdram.core.lasmicon.multiplexer import * class Refresher(Module): diff --git a/misoclib/mem/sdram/core/lasmixbar.py b/misoc/mem/sdram/core/lasmixbar.py similarity index 99% rename from misoclib/mem/sdram/core/lasmixbar.py rename to misoc/mem/sdram/core/lasmixbar.py index 56e67aa5a..cbba9499c 100644 --- a/misoclib/mem/sdram/core/lasmixbar.py +++ b/misoc/mem/sdram/core/lasmixbar.py @@ -3,7 +3,7 @@ from migen.genlib import roundrobin from migen.genlib.record import * from migen.genlib.misc import optree -from misoclib.mem.sdram.core.lasmibus import Interface +from misoc.mem.sdram.core.lasmibus import Interface def _getattr_all(l, attr): diff --git a/misoclib/mem/sdram/core/minicon/__init__.py b/misoc/mem/sdram/core/minicon/__init__.py similarity index 99% rename from misoclib/mem/sdram/core/minicon/__init__.py rename to misoc/mem/sdram/core/minicon/__init__.py index 77259a711..dd70f58cf 100644 --- a/misoclib/mem/sdram/core/minicon/__init__.py +++ b/misoc/mem/sdram/core/minicon/__init__.py @@ -3,7 +3,7 @@ from migen.bus import wishbone from migen.genlib.fsm import FSM, NextState from migen.genlib.misc import optree, WaitTimer -from misoclib.mem.sdram.phy import dfi as dfibus +from misoc.mem.sdram.phy import dfi as dfibus class _AddressSlicer: diff --git a/misoclib/mem/sdram/frontend/__init__.py b/misoc/mem/sdram/frontend/__init__.py similarity index 100% rename from misoclib/mem/sdram/frontend/__init__.py rename to misoc/mem/sdram/frontend/__init__.py diff --git a/misoclib/mem/sdram/frontend/dma_lasmi.py b/misoc/mem/sdram/frontend/dma_lasmi.py similarity index 100% rename from misoclib/mem/sdram/frontend/dma_lasmi.py rename to misoc/mem/sdram/frontend/dma_lasmi.py diff --git a/misoclib/mem/sdram/frontend/memtest.py b/misoc/mem/sdram/frontend/memtest.py similarity index 98% rename from misoclib/mem/sdram/frontend/memtest.py rename to misoc/mem/sdram/frontend/memtest.py index 790aa765b..9b3c62a3d 100644 --- a/misoclib/mem/sdram/frontend/memtest.py +++ b/misoc/mem/sdram/frontend/memtest.py @@ -3,7 +3,7 @@ from migen.genlib.misc import optree from migen.bank.description import * from migen.actorlib.spi import * -from misoclib.mem.sdram.frontend import dma_lasmi +from misoc.mem.sdram.frontend import dma_lasmi @DecorateModule(InsertReset) diff --git a/misoclib/mem/sdram/frontend/wishbone2lasmi.py b/misoc/mem/sdram/frontend/wishbone2lasmi.py similarity index 100% rename from misoclib/mem/sdram/frontend/wishbone2lasmi.py rename to misoc/mem/sdram/frontend/wishbone2lasmi.py diff --git a/misoclib/mem/sdram/module.py b/misoc/mem/sdram/module.py similarity index 99% rename from misoclib/mem/sdram/module.py rename to misoc/mem/sdram/module.py index ae265066b..f15867d8e 100644 --- a/misoclib/mem/sdram/module.py +++ b/misoc/mem/sdram/module.py @@ -17,7 +17,7 @@ from math import ceil from migen.fhdl.std import * -from misoclib.mem import sdram +from misoc.mem import sdram class SDRAMModule: diff --git a/misoclib/mem/sdram/phy/__init__.py b/misoc/mem/sdram/phy/__init__.py similarity index 100% rename from misoclib/mem/sdram/phy/__init__.py rename to misoc/mem/sdram/phy/__init__.py diff --git a/misoclib/mem/sdram/phy/dfi.py b/misoc/mem/sdram/phy/dfi.py similarity index 100% rename from misoclib/mem/sdram/phy/dfi.py rename to misoc/mem/sdram/phy/dfi.py diff --git a/misoclib/mem/sdram/phy/dfii.py b/misoc/mem/sdram/phy/dfii.py similarity index 98% rename from misoclib/mem/sdram/phy/dfii.py rename to misoc/mem/sdram/phy/dfii.py index 09ac053b1..ffbdc7dd3 100644 --- a/misoclib/mem/sdram/phy/dfii.py +++ b/misoc/mem/sdram/phy/dfii.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.bank.description import * -from misoclib.mem.sdram.phy import dfi +from misoc.mem.sdram.phy import dfi class PhaseInjector(Module, AutoCSR): diff --git a/misoclib/mem/sdram/phy/gensdrphy.py b/misoc/mem/sdram/phy/gensdrphy.py similarity index 97% rename from misoclib/mem/sdram/phy/gensdrphy.py rename to misoc/mem/sdram/phy/gensdrphy.py index 6a3e07c13..80c589d64 100644 --- a/misoclib/mem/sdram/phy/gensdrphy.py +++ b/misoc/mem/sdram/phy/gensdrphy.py @@ -25,8 +25,8 @@ from migen.fhdl.std import * from migen.genlib.record import * from migen.fhdl.specials import * -from misoclib.mem.sdram.phy.dfi import * -from misoclib.mem import sdram +from misoc.mem.sdram.phy.dfi import * +from misoc.mem import sdram class GENSDRPHY(Module): diff --git a/misoclib/mem/sdram/phy/initsequence.py b/misoc/mem/sdram/phy/initsequence.py similarity index 100% rename from misoclib/mem/sdram/phy/initsequence.py rename to misoc/mem/sdram/phy/initsequence.py diff --git a/misoclib/mem/sdram/phy/k7ddrphy.py b/misoc/mem/sdram/phy/k7ddrphy.py similarity index 99% rename from misoclib/mem/sdram/phy/k7ddrphy.py rename to misoc/mem/sdram/phy/k7ddrphy.py index d516680ad..5a2e0fc93 100644 --- a/misoclib/mem/sdram/phy/k7ddrphy.py +++ b/misoc/mem/sdram/phy/k7ddrphy.py @@ -3,8 +3,8 @@ from migen.fhdl.std import * from migen.bank.description import * -from misoclib.mem.sdram.phy.dfi import * -from misoclib.mem import sdram +from misoc.mem.sdram.phy.dfi import * +from misoc.mem import sdram class K7DDRPHY(Module, AutoCSR): diff --git a/misoclib/mem/sdram/phy/s6ddrphy.py b/misoc/mem/sdram/phy/s6ddrphy.py similarity index 99% rename from misoclib/mem/sdram/phy/s6ddrphy.py rename to misoc/mem/sdram/phy/s6ddrphy.py index f98a184be..7153f05c0 100644 --- a/misoclib/mem/sdram/phy/s6ddrphy.py +++ b/misoc/mem/sdram/phy/s6ddrphy.py @@ -19,8 +19,8 @@ from migen.fhdl.std import * from migen.genlib.record import * -from misoclib.mem.sdram.phy.dfi import * -from misoclib.mem import sdram +from misoc.mem.sdram.phy.dfi import * +from misoc.mem import sdram class S6HalfRateDDRPHY(Module): diff --git a/misoclib/mem/sdram/phy/simphy.py b/misoc/mem/sdram/phy/simphy.py similarity index 98% rename from misoclib/mem/sdram/phy/simphy.py rename to misoc/mem/sdram/phy/simphy.py index 9c1eec237..0588d082c 100644 --- a/misoclib/mem/sdram/phy/simphy.py +++ b/misoc/mem/sdram/phy/simphy.py @@ -8,8 +8,8 @@ from migen.fhdl.std import * from migen.fhdl.specials import * -from misoclib.mem.sdram.phy.dfi import * -from misoclib.mem import sdram +from misoc.mem.sdram.phy.dfi import * +from misoc.mem import sdram class Bank(Module): diff --git a/misoclib/mem/sdram/test/abstract_transactions_lasmi.py b/misoc/mem/sdram/test/abstract_transactions_lasmi.py similarity index 96% rename from misoclib/mem/sdram/test/abstract_transactions_lasmi.py rename to misoc/mem/sdram/test/abstract_transactions_lasmi.py index b53d46c2c..fd027f759 100644 --- a/misoclib/mem/sdram/test/abstract_transactions_lasmi.py +++ b/misoc/mem/sdram/test/abstract_transactions_lasmi.py @@ -2,7 +2,7 @@ from migen.fhdl.std import * from migen.bus.transactions import * from migen.sim.generic import run_simulation -from misoclib.mem.sdram.core import lasmibus +from misoc.mem.sdram.core import lasmibus def my_generator(n): diff --git a/misoclib/mem/sdram/test/bankmachine_tb.py b/misoc/mem/sdram/test/bankmachine_tb.py similarity index 92% rename from misoclib/mem/sdram/test/bankmachine_tb.py rename to misoc/mem/sdram/test/bankmachine_tb.py index ca7a16c5c..54578dcec 100644 --- a/misoclib/mem/sdram/test/bankmachine_tb.py +++ b/misoc/mem/sdram/test/bankmachine_tb.py @@ -1,8 +1,8 @@ from migen.fhdl.std import * from migen.sim.generic import run_simulation -from misoclib.mem.sdram.code import lasmibus -from misoclib.mem.sdram.core.lasmicon.bankmachine import * +from misoc.mem.sdram.code import lasmibus +from misoc.mem.sdram.core.lasmicon.bankmachine import * from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger diff --git a/misoclib/mem/sdram/test/common.py b/misoc/mem/sdram/test/common.py similarity index 98% rename from misoclib/mem/sdram/test/common.py rename to misoc/mem/sdram/test/common.py index 0f3b9c32d..6c1c09ddb 100644 --- a/misoclib/mem/sdram/test/common.py +++ b/misoc/mem/sdram/test/common.py @@ -3,7 +3,7 @@ from math import ceil from migen.fhdl.std import * -from misoclib import sdram +from misoc import sdram MHz = 1000000 clk_freq = (83 + Fraction(1, 3))*MHz diff --git a/misoclib/mem/sdram/test/lasmicon_df_tb.py b/misoc/mem/sdram/test/lasmicon_df_tb.py similarity index 90% rename from misoclib/mem/sdram/test/lasmicon_df_tb.py rename to misoc/mem/sdram/test/lasmicon_df_tb.py index 89b0d2521..bee4a7d40 100644 --- a/misoclib/mem/sdram/test/lasmicon_df_tb.py +++ b/misoc/mem/sdram/test/lasmicon_df_tb.py @@ -1,9 +1,9 @@ from migen.fhdl.std import * from migen.sim.generic import run_simulation -from misoclib.mem.sdram.core import lasmibus -from misoclib.mem.sdram.core.lasmicon import * -from misoclib.mem.sdram.frontend import dma_lasmi +from misoc.mem.sdram.core import lasmibus +from misoc.mem.sdram.core.lasmicon import * +from misoc.mem.sdram.frontend import dma_lasmi from common import sdram_phy, sdram_geom, sdram_timing, DFILogger diff --git a/misoclib/mem/sdram/test/lasmicon_tb.py b/misoc/mem/sdram/test/lasmicon_tb.py similarity index 92% rename from misoclib/mem/sdram/test/lasmicon_tb.py rename to misoc/mem/sdram/test/lasmicon_tb.py index 1169898c8..957e3e71e 100644 --- a/misoclib/mem/sdram/test/lasmicon_tb.py +++ b/misoc/mem/sdram/test/lasmicon_tb.py @@ -1,8 +1,8 @@ from migen.fhdl.std import * from migen.sim.generic import run_simulation -from misoclib.mem.sdram.core import lasmibus -from misoclib.mem.sdram.core.lasmicon import * +from misoc.mem.sdram.core import lasmibus +from misoc.mem.sdram.core.lasmicon import * from common import sdram_phy, sdram_geom, sdram_timing, DFILogger diff --git a/misoclib/mem/sdram/test/lasmicon_wb.py b/misoc/mem/sdram/test/lasmicon_wb.py similarity index 89% rename from misoclib/mem/sdram/test/lasmicon_wb.py rename to misoc/mem/sdram/test/lasmicon_wb.py index e6d967b55..425bdf71f 100644 --- a/misoclib/mem/sdram/test/lasmicon_wb.py +++ b/misoc/mem/sdram/test/lasmicon_wb.py @@ -3,9 +3,9 @@ from migen.bus import wishbone from migen.bus.transactions import * from migen.sim.generic import run_simulation -from misoclib.mem.sdram.core import lasmibus -from misoclib.mem.sdram.core.lasmicon import * -from misoclib.mem.sdram.frontend import wishbone2lasmi +from misoc.mem.sdram.core import lasmibus +from misoc.mem.sdram.core.lasmicon import * +from misoc.mem.sdram.frontend import wishbone2lasmi from common import sdram_phy, sdram_geom, sdram_timing, DFILogger diff --git a/misoclib/mem/sdram/test/minicon_tb.py b/misoc/mem/sdram/test/minicon_tb.py similarity index 97% rename from misoclib/mem/sdram/test/minicon_tb.py rename to misoc/mem/sdram/test/minicon_tb.py index 8c7f639dc..8aa4f8997 100644 --- a/misoclib/mem/sdram/test/minicon_tb.py +++ b/misoc/mem/sdram/test/minicon_tb.py @@ -4,9 +4,9 @@ from migen.bus import wishbone from migen.sim.generic import Simulator from migen.sim import icarus from mibuild.platforms import papilio_pro as board -from misoclib import sdram -from misoclib.mem.sdram.core.minicon import Minicon -from misoclib.mem.sdram.phy import gensdrphy +from misoc import sdram +from misoc.mem.sdram.core.minicon import Minicon +from misoc.mem.sdram.phy import gensdrphy from itertools import chain from os.path import isfile import sys diff --git a/misoclib/mem/sdram/test/refresher.py b/misoc/mem/sdram/test/refresher.py similarity index 95% rename from misoclib/mem/sdram/test/refresher.py rename to misoc/mem/sdram/test/refresher.py index 06367230f..4a13c19e3 100644 --- a/misoclib/mem/sdram/test/refresher.py +++ b/misoc/mem/sdram/test/refresher.py @@ -3,7 +3,7 @@ from random import Random from migen.fhdl.std import * from migen.sim.generic import run_simulation -from misoclib.mem.sdram.core.lasmicon.refresher import * +from misoc.mem.sdram.core.lasmicon.refresher import * from common import CommandLogger diff --git a/misoclib/mxcrg.v b/misoc/mxcrg.v similarity index 100% rename from misoclib/mxcrg.v rename to misoc/mxcrg.v diff --git a/misoclib/soc/__init__.py b/misoc/soc/__init__.py similarity index 98% rename from misoclib/soc/__init__.py rename to misoc/soc/__init__.py index ef7c45454..889be51da 100644 --- a/misoclib/soc/__init__.py +++ b/misoc/soc/__init__.py @@ -4,10 +4,10 @@ from migen.fhdl.std import * from migen.bank import csrgen from migen.bus import wishbone, csr, wishbone2csr -from misoclib.com.uart.phy import UARTPHY -from misoclib.com import uart -from misoclib.cpu import lm32, mor1kx -from misoclib.cpu import identifier, timer +from misoc.com.uart.phy import UARTPHY +from misoc.com import uart +from misoc.cpu import lm32, mor1kx +from misoc.cpu import identifier, timer def mem_decoder(address, start=26, end=29): diff --git a/misoclib/soc/cpuif.py b/misoc/soc/cpuif.py similarity index 100% rename from misoclib/soc/cpuif.py rename to misoc/soc/cpuif.py diff --git a/misoclib/soc/sdram.py b/misoc/soc/sdram.py similarity index 95% rename from misoclib/soc/sdram.py rename to misoc/soc/sdram.py index 4687c0344..d46beb1cc 100644 --- a/misoclib/soc/sdram.py +++ b/misoc/soc/sdram.py @@ -2,11 +2,11 @@ from migen.fhdl.std import * from migen.bus import wishbone from migen.genlib.record import * -from misoclib.mem.sdram.core import SDRAMCore -from misoclib.mem.sdram.core.lasmicon import LASMIconSettings -from misoclib.mem.sdram.core.minicon import MiniconSettings -from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi -from misoclib.soc import SoC +from misoc.mem.sdram.core import SDRAMCore +from misoc.mem.sdram.core.lasmicon import LASMIconSettings +from misoc.mem.sdram.core.minicon import MiniconSettings +from misoc.mem.sdram.frontend import memtest, wishbone2lasmi +from misoc.soc import SoC class SDRAMSoC(SoC): diff --git a/misoclib/tools/__init__.py b/misoc/tools/__init__.py similarity index 100% rename from misoclib/tools/__init__.py rename to misoc/tools/__init__.py diff --git a/misoclib/tools/wishbone.py b/misoc/tools/wishbone.py similarity index 100% rename from misoclib/tools/wishbone.py rename to misoc/tools/wishbone.py diff --git a/misoclib/video/__init__.py b/misoc/video/__init__.py similarity index 100% rename from misoclib/video/__init__.py rename to misoc/video/__init__.py diff --git a/misoclib/video/dvisampler/__init__.py b/misoc/video/dvisampler/__init__.py similarity index 83% rename from misoclib/video/dvisampler/__init__.py rename to misoc/video/dvisampler/__init__.py index 1f56af0f2..1670ccfa7 100644 --- a/misoclib/video/dvisampler/__init__.py +++ b/misoc/video/dvisampler/__init__.py @@ -1,15 +1,15 @@ from migen.fhdl.std import * from migen.bank.description import AutoCSR -from misoclib.video.dvisampler.edid import EDID -from misoclib.video.dvisampler.clocking import Clocking -from misoclib.video.dvisampler.datacapture import DataCapture -from misoclib.video.dvisampler.charsync import CharSync -from misoclib.video.dvisampler.wer import WER -from misoclib.video.dvisampler.decoding import Decoding -from misoclib.video.dvisampler.chansync import ChanSync -from misoclib.video.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction -from misoclib.video.dvisampler.dma import DMA +from misoc.video.dvisampler.edid import EDID +from misoc.video.dvisampler.clocking import Clocking +from misoc.video.dvisampler.datacapture import DataCapture +from misoc.video.dvisampler.charsync import CharSync +from misoc.video.dvisampler.wer import WER +from misoc.video.dvisampler.decoding import Decoding +from misoc.video.dvisampler.chansync import ChanSync +from misoc.video.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction +from misoc.video.dvisampler.dma import DMA class DVISampler(Module, AutoCSR): diff --git a/misoclib/video/dvisampler/analysis.py b/misoc/video/dvisampler/analysis.py similarity index 99% rename from misoclib/video/dvisampler/analysis.py rename to misoc/video/dvisampler/analysis.py index ccc7667d0..77003c727 100644 --- a/misoclib/video/dvisampler/analysis.py +++ b/misoc/video/dvisampler/analysis.py @@ -5,7 +5,7 @@ from migen.genlib.record import Record from migen.bank.description import * from migen.flow.actor import * -from misoclib.video.dvisampler.common import channel_layout +from misoc.video.dvisampler.common import channel_layout class SyncPolarity(Module): diff --git a/misoclib/video/dvisampler/chansync.py b/misoc/video/dvisampler/chansync.py similarity index 98% rename from misoclib/video/dvisampler/chansync.py rename to misoc/video/dvisampler/chansync.py index 0e5d0d6fc..b83b8188d 100644 --- a/misoclib/video/dvisampler/chansync.py +++ b/misoc/video/dvisampler/chansync.py @@ -5,7 +5,7 @@ from migen.genlib.record import Record, layout_len from migen.genlib.misc import optree from migen.bank.description import * -from misoclib.video.dvisampler.common import channel_layout +from misoc.video.dvisampler.common import channel_layout class _SyncBuffer(Module): diff --git a/misoclib/video/dvisampler/charsync.py b/misoc/video/dvisampler/charsync.py similarity index 96% rename from misoclib/video/dvisampler/charsync.py rename to misoc/video/dvisampler/charsync.py index 343303e2b..102da27d7 100644 --- a/misoclib/video/dvisampler/charsync.py +++ b/misoc/video/dvisampler/charsync.py @@ -3,7 +3,7 @@ from migen.genlib.cdc import MultiReg from migen.genlib.misc import optree from migen.bank.description import * -from misoclib.video.dvisampler.common import control_tokens +from misoc.video.dvisampler.common import control_tokens class CharSync(Module, AutoCSR): diff --git a/misoclib/video/dvisampler/clocking.py b/misoc/video/dvisampler/clocking.py similarity index 100% rename from misoclib/video/dvisampler/clocking.py rename to misoc/video/dvisampler/clocking.py diff --git a/misoclib/video/dvisampler/common.py b/misoc/video/dvisampler/common.py similarity index 100% rename from misoclib/video/dvisampler/common.py rename to misoc/video/dvisampler/common.py diff --git a/misoclib/video/dvisampler/datacapture.py b/misoc/video/dvisampler/datacapture.py similarity index 100% rename from misoclib/video/dvisampler/datacapture.py rename to misoc/video/dvisampler/datacapture.py diff --git a/misoclib/video/dvisampler/debug.py b/misoc/video/dvisampler/debug.py similarity index 88% rename from misoclib/video/dvisampler/debug.py rename to misoc/video/dvisampler/debug.py index 6cbc5a3b5..67af06e6e 100644 --- a/misoclib/video/dvisampler/debug.py +++ b/misoc/video/dvisampler/debug.py @@ -4,10 +4,10 @@ from migen.genlib.record import layout_len from migen.bank.description import AutoCSR from migen.actorlib import structuring, spi -from misoclib.mem.sdram.frontend import dma_lasmi -from misoclib.video.dvisampler.edid import EDID -from misoclib.video.dvisampler.clocking import Clocking -from misoclib.video.dvisampler.datacapture import DataCapture +from misoc.mem.sdram.frontend import dma_lasmi +from misoc.video.dvisampler.edid import EDID +from misoc.video.dvisampler.clocking import Clocking +from misoc.video.dvisampler.datacapture import DataCapture class RawDVISampler(Module, AutoCSR): diff --git a/misoclib/video/dvisampler/decoding.py b/misoc/video/dvisampler/decoding.py similarity index 90% rename from misoclib/video/dvisampler/decoding.py rename to misoc/video/dvisampler/decoding.py index db0b48e12..2d0ddbf43 100644 --- a/misoclib/video/dvisampler/decoding.py +++ b/misoc/video/dvisampler/decoding.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.genlib.record import Record -from misoclib.video.dvisampler.common import control_tokens, channel_layout +from misoc.video.dvisampler.common import control_tokens, channel_layout class Decoding(Module): diff --git a/misoclib/video/dvisampler/dma.py b/misoc/video/dvisampler/dma.py similarity index 99% rename from misoclib/video/dvisampler/dma.py rename to misoc/video/dvisampler/dma.py index 5f4775263..75458df74 100644 --- a/misoclib/video/dvisampler/dma.py +++ b/misoc/video/dvisampler/dma.py @@ -4,7 +4,7 @@ from migen.bank.description import * from migen.bank.eventmanager import * from migen.flow.actor import * -from misoclib.mem.sdram.frontend import dma_lasmi +from misoc.mem.sdram.frontend import dma_lasmi # Slot status: EMPTY=0 LOADED=1 PENDING=2 diff --git a/misoclib/video/dvisampler/edid.py b/misoc/video/dvisampler/edid.py similarity index 100% rename from misoclib/video/dvisampler/edid.py rename to misoc/video/dvisampler/edid.py diff --git a/misoclib/video/dvisampler/wer.py b/misoc/video/dvisampler/wer.py similarity index 97% rename from misoclib/video/dvisampler/wer.py rename to misoc/video/dvisampler/wer.py index 17399c235..310e6d48d 100644 --- a/misoclib/video/dvisampler/wer.py +++ b/misoc/video/dvisampler/wer.py @@ -3,7 +3,7 @@ from migen.bank.description import * from migen.genlib.misc import optree from migen.genlib.cdc import PulseSynchronizer -from misoclib.video.dvisampler.common import control_tokens +from misoc.video.dvisampler.common import control_tokens class WER(Module, AutoCSR): diff --git a/misoclib/video/framebuffer/__init__.py b/misoc/video/framebuffer/__init__.py similarity index 85% rename from misoclib/video/framebuffer/__init__.py rename to misoc/video/framebuffer/__init__.py index 10ea20155..eec9404ba 100644 --- a/misoclib/video/framebuffer/__init__.py +++ b/misoc/video/framebuffer/__init__.py @@ -4,9 +4,9 @@ from migen.flow import plumbing from migen.bank.description import AutoCSR from migen.actorlib import structuring, misc -from misoclib.mem.sdram.frontend import dma_lasmi -from misoclib.video.framebuffer.format import bpp, pixel_layout, FrameInitiator, VTG -from misoclib.video.framebuffer.phy import Driver +from misoc.mem.sdram.frontend import dma_lasmi +from misoc.video.framebuffer.format import bpp, pixel_layout, FrameInitiator, VTG +from misoc.video.framebuffer.phy import Driver class Framebuffer(Module, AutoCSR): diff --git a/misoclib/video/framebuffer/dvi.py b/misoc/video/framebuffer/dvi.py similarity index 100% rename from misoclib/video/framebuffer/dvi.py rename to misoc/video/framebuffer/dvi.py diff --git a/misoclib/video/framebuffer/format.py b/misoc/video/framebuffer/format.py similarity index 100% rename from misoclib/video/framebuffer/format.py rename to misoc/video/framebuffer/format.py diff --git a/misoclib/video/framebuffer/phy.py b/misoc/video/framebuffer/phy.py similarity index 98% rename from misoclib/video/framebuffer/phy.py rename to misoc/video/framebuffer/phy.py index d4958ff98..d77426c55 100644 --- a/misoclib/video/framebuffer/phy.py +++ b/misoc/video/framebuffer/phy.py @@ -4,8 +4,8 @@ from migen.genlib.cdc import MultiReg from migen.bank.description import * from migen.flow.actor import * -from misoclib.video.framebuffer.format import bpc_phy, phy_layout -from misoclib.video.framebuffer import dvi +from misoc.video.framebuffer.format import bpc_phy, phy_layout +from misoc.video.framebuffer import dvi class _FIFO(Module): diff --git a/setup.py b/setup.py index 41af6c81c..52fd0aa59 100644 --- a/setup.py +++ b/setup.py @@ -1,38 +1,38 @@ -#!/usr/bin/env python3 - -import sys -import os -from setuptools import setup -from setuptools import find_packages - -here = os.path.abspath(os.path.dirname(__file__)) -README = open(os.path.join(here, "README")).read() - -required_version = (3, 3) -if sys.version_info < required_version: - raise SystemExit("MiSoC requires python {0} or greater".format( - ".".join(map(str, required_version)))) - -setup( - name="misoclib", - version="unknown", - description="a high performance and small footprint SoC based on Migen", - long_description=README, - author="Sebastien Bourdeauducq", - author_email="sb@m-labs.hk", - url="http://m-labs.hk", - download_url="https://github.com/m-labs/misoc", - packages=find_packages(here), - license="BSD", - platforms=["Any"], - keywords="HDL ASIC FPGA hardware design", - classifiers=[ - "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)", - "Environment :: Console", - "Development Status :: Alpha", - "Intended Audience :: Developers", - "License :: OSI Approved :: BSD License", - "Operating System :: OS Independent", - "Programming Language :: Python", - ], -) +#!/usr/bin/env python3 + +import sys +import os +from setuptools import setup +from setuptools import find_packages + +here = os.path.abspath(os.path.dirname(__file__)) +README = open(os.path.join(here, "README")).read() + +required_version = (3, 3) +if sys.version_info < required_version: + raise SystemExit("MiSoC requires python {0} or greater".format( + ".".join(map(str, required_version)))) + +setup( + name="misoc", + version="unknown", + description="a high performance and small footprint SoC based on Migen", + long_description=README, + author="Sebastien Bourdeauducq", + author_email="sb@m-labs.hk", + url="http://m-labs.hk", + download_url="https://github.com/m-labs/misoc", + packages=find_packages(here), + license="BSD", + platforms=["Any"], + keywords="HDL ASIC FPGA hardware design", + classifiers=[ + "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)", + "Environment :: Console", + "Development Status :: Alpha", + "Intended Audience :: Developers", + "License :: OSI Approved :: BSD License", + "Operating System :: OS Independent", + "Programming Language :: Python", + ], +) diff --git a/software/common.mak b/software/common.mak index 72f42fcbf..cff9bbd3a 100644 --- a/software/common.mak +++ b/software/common.mak @@ -21,7 +21,7 @@ AR_quiet = @echo " AR " $@ && $(AR_normal) LD_quiet = @echo " LD " $@ && $(LD_normal) OBJCOPY_quiet = @echo " OBJCOPY " $@ && $(OBJCOPY_normal) -MSC_GIT_ID := $(shell cd $(MSCDIR) && $(PYTHON) -c "from misoclib.cpu.identifier import get_id; print(hex(get_id()), end='')") +MSC_GIT_ID := $(shell cd $(MSCDIR) && $(PYTHON) -c "from misoc.cpu.identifier import get_id; print(hex(get_id()), end='')") ifeq ($(V),1) CC = $(CC_normal) diff --git a/targets/de0nano.py b/targets/de0nano.py index c6f733d3c..d823b0a67 100644 --- a/targets/de0nano.py +++ b/targets/de0nano.py @@ -1,9 +1,9 @@ from migen.fhdl.std import * -from misoclib.mem.sdram.module import IS42S16160 -from misoclib.mem.sdram.phy import gensdrphy -from misoclib.mem.sdram.core.lasmicon import LASMIconSettings -from misoclib.soc.sdram import SDRAMSoC +from misoc.mem.sdram.module import IS42S16160 +from misoc.mem.sdram.phy import gensdrphy +from misoc.mem.sdram.core.lasmicon import LASMIconSettings +from misoc.soc.sdram import SDRAMSoC class _PLL(Module): diff --git a/targets/kc705.py b/targets/kc705.py index 2604ae94d..e9cf70e48 100644 --- a/targets/kc705.py +++ b/targets/kc705.py @@ -1,15 +1,15 @@ from migen.fhdl.std import * from migen.genlib.resetsync import AsyncResetSynchronizer -from misoclib.mem.sdram.module import MT8JTF12864 -from misoclib.mem.sdram.phy import k7ddrphy -from misoclib.mem.sdram.core.lasmicon import LASMIconSettings -from misoclib.mem.flash import spiflash -from misoclib.soc import mem_decoder -from misoclib.soc.sdram import SDRAMSoC +from misoc.mem.sdram.module import MT8JTF12864 +from misoc.mem.sdram.phy import k7ddrphy +from misoc.mem.sdram.core.lasmicon import LASMIconSettings +from misoc.mem.flash import spiflash +from misoc.soc import mem_decoder +from misoc.soc.sdram import SDRAMSoC -from misoclib.com.liteethmini.phy import LiteEthPHY -from misoclib.com.liteethmini.mac import LiteEthMAC +from misoc.com.liteethmini.phy import LiteEthPHY +from misoc.com.liteethmini.mac import LiteEthMAC class _CRG(Module): diff --git a/targets/minispartan6.py b/targets/minispartan6.py index ffea2f354..ff5e4b827 100644 --- a/targets/minispartan6.py +++ b/targets/minispartan6.py @@ -4,10 +4,10 @@ from migen.fhdl.std import * from migen.genlib.resetsync import AsyncResetSynchronizer from migen.actorlib.fifo import SyncFIFO -from misoclib.mem.sdram.module import AS4C16M16 -from misoclib.mem.sdram.phy import gensdrphy -from misoclib.mem.sdram.core.lasmicon import LASMIconSettings -from misoclib.soc.sdram import SDRAMSoC +from misoc.mem.sdram.module import AS4C16M16 +from misoc.mem.sdram.phy import gensdrphy +from misoc.mem.sdram.core.lasmicon import LASMIconSettings +from misoc.soc.sdram import SDRAMSoC class _CRG(Module): def __init__(self, platform, clk_freq): diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index 0602ac467..fcd8481c4 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -5,16 +5,16 @@ from math import ceil from migen.fhdl.std import * from mibuild.generic_platform import ConstraintError -from misoclib.mem.sdram.module import MT46V32M16 -from misoclib.mem.sdram.phy import s6ddrphy -from misoclib.mem.sdram.core.lasmicon import LASMIconSettings -from misoclib.mem.flash import norflash16 -from misoclib.video import framebuffer -from misoclib.soc import mem_decoder -from misoclib.soc.sdram import SDRAMSoC -from misoclib.com import gpio -from misoclib.com.liteethmini.phy import LiteEthPHY -from misoclib.com.liteethmini.mac import LiteEthMAC +from misoc.mem.sdram.module import MT46V32M16 +from misoc.mem.sdram.phy import s6ddrphy +from misoc.mem.sdram.core.lasmicon import LASMIconSettings +from misoc.mem.flash import norflash16 +from misoc.video import framebuffer +from misoc.soc import mem_decoder +from misoc.soc.sdram import SDRAMSoC +from misoc.com import gpio +from misoc.com.liteethmini.phy import LiteEthPHY +from misoc.com.liteethmini.mac import LiteEthMAC class _MXCRG(Module): @@ -104,7 +104,7 @@ class BaseSoC(SDRAMSoC): INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2"; INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3"; """) - platform.add_source(os.path.join("misoclib", "mxcrg.v")) + platform.add_source(os.path.join("misoc", "mxcrg.v")) class MiniSoC(BaseSoC): diff --git a/targets/pipistrello.py b/targets/pipistrello.py index fd9bd1cbe..668be1de0 100644 --- a/targets/pipistrello.py +++ b/targets/pipistrello.py @@ -3,11 +3,11 @@ from fractions import Fraction from migen.fhdl.std import * from migen.genlib.resetsync import AsyncResetSynchronizer -from misoclib.mem.sdram.module import MT46H32M16 -from misoclib.mem.sdram.phy import s6ddrphy -from misoclib.mem.sdram.core.lasmicon import LASMIconSettings -from misoclib.mem.flash import spiflash -from misoclib.soc.sdram import SDRAMSoC +from misoc.mem.sdram.module import MT46H32M16 +from misoc.mem.sdram.phy import s6ddrphy +from misoc.mem.sdram.core.lasmicon import LASMIconSettings +from misoc.mem.flash import spiflash +from misoc.soc.sdram import SDRAMSoC class _CRG(Module): diff --git a/targets/ppro.py b/targets/ppro.py index 96eaf221b..1b5f43bf0 100644 --- a/targets/ppro.py +++ b/targets/ppro.py @@ -3,11 +3,11 @@ from fractions import Fraction from migen.fhdl.std import * from migen.genlib.resetsync import AsyncResetSynchronizer -from misoclib.mem.sdram.module import MT48LC4M16 -from misoclib.mem.sdram.phy import gensdrphy -from misoclib.mem.sdram.core.lasmicon import LASMIconSettings -from misoclib.mem.flash import spiflash -from misoclib.soc.sdram import SDRAMSoC +from misoc.mem.sdram.module import MT48LC4M16 +from misoc.mem.sdram.phy import gensdrphy +from misoc.mem.sdram.core.lasmicon import LASMIconSettings +from misoc.mem.flash import spiflash +from misoc.soc.sdram import SDRAMSoC class _CRG(Module): diff --git a/targets/simple.py b/targets/simple.py index ffa041521..b28d5917f 100644 --- a/targets/simple.py +++ b/targets/simple.py @@ -2,9 +2,9 @@ from migen.fhdl.std import * from migen.bus import wishbone from migen.genlib.io import CRG -from misoclib.soc import SoC, mem_decoder -from misoclib.com.liteethmini.phy import LiteEthPHY -from misoclib.com.liteethmini.mac import LiteEthMAC +from misoc.soc import SoC, mem_decoder +from misoc.com.liteethmini.phy import LiteEthPHY +from misoc.com.liteethmini.mac import LiteEthMAC class BaseSoC(SoC): diff --git a/targets/versa.py b/targets/versa.py index e1c376efa..fd787476a 100644 --- a/targets/versa.py +++ b/targets/versa.py @@ -2,7 +2,7 @@ from migen.fhdl.std import * from migen.bus import wishbone from migen.genlib.io import CRG -from misoclib.soc import SoC +from misoc.soc import SoC class BaseSoC(SoC):