From bd96b47041027d7e78e60a84d8fa78032aa4fd18 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 6 Jun 2024 16:36:56 +0200 Subject: [PATCH] Vexii fix mem data width --- litex/soc/cores/cpu/vexiiriscv/core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index fac7e1319..4b38cd83a 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -158,8 +158,8 @@ class VexiiRiscv(CPU): if args.cpu_variant in ["linux", "debian"]: VexiiRiscv.vexii_args += " --with-rva --with-supervisor" - VexiiRiscv.vexii_args += " --fetch-l1-ways=4" - VexiiRiscv.vexii_args += " --lsu-l1-ways=4" + VexiiRiscv.vexii_args += " --fetch-l1-ways=4 --fetch-l1-mem-data-width-min=64" + VexiiRiscv.vexii_args += " --lsu-l1-ways=4 --lsu-l1-mem-data-width-min=64" if args.cpu_variant in ["debian"]: VexiiRiscv.vexii_args += " --xlen=64 --with-rvc --with-rvf --with-rvd --fma-reduced-accuracy"